^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Common Clock Framework support for S3C2410 and following SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/samsung.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LOCKTIME 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPLLCON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UPLLCON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKCON 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKSLOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKDIVN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CAMDIVN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* the soc types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum supported_socs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) S3C2410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) S3C2440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) S3C2442,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* list of PLLs to be registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum s3c2410_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mpll, upll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned long s3c2410_clk_regs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) LOCKTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) UPLLCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CLKCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CLKSLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CLKDIVN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CAMDIVN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PNAME(fclk_p) = { "mpll", "div_slow" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct clk_div_table divslow_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .val = 3, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .val = 4, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .val = 5, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .val = 6, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .val = 7, .div = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* should be added _after_ the soc-specific clocks are created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ALIAS(PCLK_ADC, NULL, "adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ALIAS(PCLK_RTC, NULL, "rtc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ALIAS(PCLK_PWM, NULL, "timers"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ALIAS(HCLK_LCD, NULL, "lcd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ALIAS(HCLK_USBD, NULL, "usb-device"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ALIAS(HCLK_USBH, NULL, "usb-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ALIAS(UCLK, NULL, "usb-bus-host"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ALIAS(UCLK, NULL, "usb-bus-gadget"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ALIAS(ARMCLK, NULL, "armclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ALIAS(UCLK, NULL, "uclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ALIAS(HCLK, NULL, "hclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ALIAS(MPLL, NULL, "mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ALIAS(FCLK, NULL, "fclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ALIAS(PCLK, NULL, "watchdog"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ALIAS(PCLK_SDI, NULL, "sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ALIAS(HCLK_NAND, NULL, "nand"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ALIAS(PCLK_I2S, NULL, "iis"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ALIAS(PCLK_I2C, NULL, "i2c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* S3C2410 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* sorted in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* 2410A extras */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 2410 common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct samsung_pll_clock s3c2410_plls[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LOCKTIME, MPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LOCKTIME, UPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct samsung_div_clock s3c2410_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * armclk is directly supplied by the fclk, without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * switching possibility like on the s3c244x below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* uclk is fed from the unmodified upll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ALIAS(UCLK, NULL, "clk_uart_baud1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* S3C244x specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* sorted in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LOCKTIME, MPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) LOCKTIME, UPLLCON, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PNAME(armclk_p) = { "fclk", "hclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct clk_div_table div_hclk_4_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .val = 0, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .val = 1, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct clk_div_table div_hclk_3_d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .val = 0, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { .val = 1, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ALIAS(HCLK_CAM, NULL, "camif"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ALIAS(CAMIF, NULL, "camif-upll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* S3C2440 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct samsung_gate_clock s3c2440_gates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* S3C2442 specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FFACTOR(0, "upll_3", "upll", 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * fixed rate clocks generated outside the soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Only necessary until the devicetree-move is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define XTI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FRATE(XTI, "xti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void __init s3c2410_common_clk_register_fixed_ext(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct samsung_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long xti_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) s3c2410_common_frate_clks[0].fixed_rate = xti_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ARRAY_SIZE(s3c2410_common_frate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) samsung_clk_register_alias(ctx, &xti_alias, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int current_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ctx = samsung_clk_init(np, reg_base, NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Register external clocks only in non-dt cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (current_soc == S3C2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (_get_rate("xti") == 12 * MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Register PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) samsung_clk_register_pll(ctx, s3c2410_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ARRAY_SIZE(s3c2410_plls), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else { /* S3C2440, S3C2442 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (_get_rate("xti") == 12 * MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * plls follow different calculation schemes, with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * upll following the same scheme as the s3c2410 plls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) s3c244x_common_plls[mpll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pll_s3c244x_12mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) s3c244x_common_plls[upll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pll_s3c2410_12mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Register PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) samsung_clk_register_pll(ctx, s3c244x_common_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ARRAY_SIZE(s3c244x_common_plls), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Register common internal clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) samsung_clk_register_mux(ctx, s3c2410_common_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ARRAY_SIZE(s3c2410_common_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) samsung_clk_register_div(ctx, s3c2410_common_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ARRAY_SIZE(s3c2410_common_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) samsung_clk_register_gate(ctx, s3c2410_common_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ARRAY_SIZE(s3c2410_common_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (current_soc == S3C2440 || current_soc == S3C2442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) samsung_clk_register_div(ctx, s3c244x_common_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ARRAY_SIZE(s3c244x_common_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) samsung_clk_register_gate(ctx, s3c244x_common_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ARRAY_SIZE(s3c244x_common_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) samsung_clk_register_mux(ctx, s3c244x_common_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ARRAY_SIZE(s3c244x_common_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ARRAY_SIZE(s3c244x_common_ffactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Register SoC-specific clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) switch (current_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case S3C2410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) samsung_clk_register_div(ctx, s3c2410_dividers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ARRAY_SIZE(s3c2410_dividers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ARRAY_SIZE(s3c2410_ffactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) samsung_clk_register_alias(ctx, s3c2410_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ARRAY_SIZE(s3c2410_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case S3C2440:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) samsung_clk_register_mux(ctx, s3c2440_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ARRAY_SIZE(s3c2440_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) samsung_clk_register_gate(ctx, s3c2440_gates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ARRAY_SIZE(s3c2440_gates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case S3C2442:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) samsung_clk_register_mux(ctx, s3c2442_muxes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ARRAY_SIZE(s3c2442_muxes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ARRAY_SIZE(s3c2442_ffactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Register common aliases at the end, as some of the aliased clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * are SoC specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) samsung_clk_register_alias(ctx, s3c2410_common_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ARRAY_SIZE(s3c2410_common_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (current_soc == S3C2440 || current_soc == S3C2442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) samsung_clk_register_alias(ctx, s3c244x_common_aliases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ARRAY_SIZE(s3c244x_common_aliases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ARRAY_SIZE(s3c2410_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void __init s3c2410_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) s3c2410_common_clk_init(np, 0, S3C2410, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void __init s3c2440_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) s3c2410_common_clk_init(np, 0, S3C2440, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void __init s3c2442_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s3c2410_common_clk_init(np, 0, S3C2442, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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