^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Common Clock Framework support for s3c24xx external clock output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_data/clk-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MUX_DCLK0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MUX_DCLK1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DIV_DCLK0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DIV_DCLK1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GATE_DCLK0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GATE_DCLK1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MUX_CLKOUT0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUX_CLKOUT1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum supported_socs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) S3C2410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) S3C2412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) S3C2440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) S3C2443,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct s3c24xx_dclk_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char **clkout0_parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int clkout0_num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const char **clkout1_parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int clkout1_num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const char **mux_parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int mux_num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Clock for output-parent selection in misccr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct s3c24xx_clkout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int (*modify_misccr)(unsigned int clr, unsigned int chg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val = clkout->modify_misccr(0, 0) >> clkout->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val >>= clkout->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val &= clkout->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (val >= num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clkout->modify_misccr((clkout->mask << clkout->shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (index << clkout->shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct clk_ops s3c24xx_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .get_parent = s3c24xx_clkout_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .set_parent = s3c24xx_clkout_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const char *name, const char **parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 shift, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct s3c2410_clk_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct s3c24xx_clkout *clkout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* allocate the clkout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!clkout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) init.ops = &s3c24xx_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clkout->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clkout->mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clkout->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clkout->modify_misccr = pdata->modify_misccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = clk_hw_register(dev, &clkout->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return &clkout->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * dclk and clkout init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct s3c24xx_dclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct notifier_block dclk0_div_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct notifier_block dclk1_div_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) spinlock_t dclk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long reg_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* clk_data must be the last entry in the structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_hw_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define to_s3c24xx_dclk0(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define to_s3c24xx_dclk1(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "gate_dclk0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "gate_dclk1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "hclk", "pclk", "gate_dclk0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "gate_dclk1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "gate_dclk0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "hclk", "pclk", "gate_dclk1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "gate_dclk0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "hclk", "pclk", "gate_dclk1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DCLKCON_DCLK_DIV_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DCLKCON_DCLK0_DIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DCLKCON_DCLK0_CMP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DCLKCON_DCLK1_DIV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DCLKCON_DCLK1_CMP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int div_shift, int cmp_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 dclk_con, div, cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dclk_con = readl_relaxed(s3c24xx_dclk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cmp = ((div + 1) / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dclk_con |= (cmp << cmp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel_relaxed(dclk_con, s3c24xx_dclk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (event == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) s3c24xx_dclk_update_cmp(s3c24xx_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (event == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) s3c24xx_dclk_update_cmp(s3c24xx_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int s3c24xx_dclk_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int s3c24xx_dclk_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int s3c24xx_dclk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct s3c24xx_dclk *s3c24xx_dclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct s3c24xx_dclk_drv_data *dclk_variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk_hw **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) s3c24xx_dclk = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct_size(s3c24xx_dclk, clk_data.hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DCLK_MAX_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!s3c24xx_dclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk_table = s3c24xx_dclk->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) s3c24xx_dclk->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) platform_set_drvdata(pdev, s3c24xx_dclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spin_lock_init(&s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) s3c24xx_dclk->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (IS_ERR(s3c24xx_dclk->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return PTR_ERR(s3c24xx_dclk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dclk_variant = (struct s3c24xx_dclk_drv_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dclk_variant->mux_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dclk_variant->mux_num_parents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) s3c24xx_dclk->base, 1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dclk_variant->mux_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dclk_variant->mux_num_parents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) s3c24xx_dclk->base, 17, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "mux_dclk0", 0, s3c24xx_dclk->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 4, 4, 0, &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "mux_dclk1", 0, s3c24xx_dclk->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 20, 4, 0, &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "div_dclk0", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) s3c24xx_dclk->base, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "div_dclk1", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) s3c24xx_dclk->base, 16, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) &s3c24xx_dclk->dclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "clkout0", dclk_variant->clkout0_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dclk_variant->clkout0_num_parents, 4, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "clkout1", dclk_variant->clkout1_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dclk_variant->clkout1_num_parents, 8, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < DCLK_MAX_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (IS_ERR(clk_table[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(&pdev->dev, "clock %d failed to register\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = PTR_ERR(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "clkout0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "clkout1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) s3c24xx_dclk0_div_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) s3c24xx_dclk1_div_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &s3c24xx_dclk->dclk0_div_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) &s3c24xx_dclk->dclk1_div_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto err_dclk_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err_dclk_notify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &s3c24xx_dclk->dclk0_div_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err_clk_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < DCLK_MAX_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (clk_table[i] && !IS_ERR(clk_table[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_hw_unregister(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int s3c24xx_dclk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &s3c24xx_dclk->dclk1_div_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &s3c24xx_dclk->dclk0_div_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < DCLK_MAX_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk_hw_unregister(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct s3c24xx_dclk_drv_data dclk_variants[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [S3C2410] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .clkout0_parent_names = clkout0_s3c2410_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .clkout1_parent_names = clkout1_s3c2410_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mux_parent_names = dclk_s3c2410_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [S3C2412] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .clkout0_parent_names = clkout0_s3c2412_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .clkout1_parent_names = clkout1_s3c2412_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .mux_parent_names = dclk_s3c2410_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [S3C2440] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .clkout0_parent_names = clkout0_s3c2440_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .clkout1_parent_names = clkout1_s3c2440_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mux_parent_names = dclk_s3c2410_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [S3C2443] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .clkout0_parent_names = clkout0_s3c2443_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .clkout1_parent_names = clkout1_s3c2443_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .mux_parent_names = dclk_s3c2443_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "s3c2410-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "s3c2412-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "s3c2440-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .name = "s3c2443-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct platform_driver s3c24xx_dclk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "s3c24xx-dclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pm = &s3c24xx_dclk_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .probe = s3c24xx_dclk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .remove = s3c24xx_dclk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .id_table = s3c24xx_dclk_driver_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) module_platform_driver(s3c24xx_dclk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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