^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for all PLL's in Samsung platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __SAMSUNG_CLK_PLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SAMSUNG_CLK_PLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum samsung_pll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) pll_2126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) pll_3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) pll_35xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) pll_36xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) pll_2550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) pll_2650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) pll_4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pll_4502,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pll_4508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) pll_4600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pll_4650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pll_4650c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pll_6552,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pll_6552_s3c2416,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) pll_6553,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pll_s3c2410_mpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) pll_s3c2410_upll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pll_s3c2440_mpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pll_2550x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pll_2550xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) pll_2650x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pll_2650xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pll_1450x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pll_1451x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) pll_1452x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pll_1460x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) _m, _p, _s, 0, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) _m + 8, _p + 2, _s, 0, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 2 * (_m + 8), _p + 2, _s, 0, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) _m, _p, _s, _k, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .kdiv = (_k), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) _m, _p, _s - 1, 0, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .afc = (_afc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) _m, _p, _s, _k, 16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .kdiv = (_k), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .vsel = (_vsel), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .rate = PLL_VALID_RATE(_fin, _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) _m, _p, _s, _k, 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .mdiv = (_m), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pdiv = (_p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .sdiv = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .kdiv = (_k), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .mfr = (_mfr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mrr = (_mrr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .vsel = (_vsel), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* NOTE: Rate table should be kept sorted in descending order. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct samsung_pll_rate_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int sdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int kdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int afc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int mfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int mrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif /* __SAMSUNG_CLK_PLL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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