^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/exynos7-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Register Offset definitions for CMU_TOPC (0x10570000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CC_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BUS0_PLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BUS1_DPLL_LOCK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MFC_PLL_LOCK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AUD_PLL_LOCK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CC_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BUS0_PLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BUS1_DPLL_CON0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MFC_PLL_CON0 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AUD_PLL_CON0 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MUX_SEL_TOPC0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUX_SEL_TOPC1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUX_SEL_TOPC2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUX_SEL_TOPC3 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DIV_TOPC0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DIV_TOPC1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DIV_TOPC3 0x060C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ENABLE_ACLK_TOPC0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ENABLE_ACLK_TOPC1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ENABLE_SCLK_TOPC1 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FFACTOR(0, "ffac_topc_bus0_pll_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "ffac_topc_bus0_pll_div2", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* List of parent clocks for Muxes in CMU_TOPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "mout_topc_mfc_pll_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "ffac_topc_bus1_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "ffac_topc_cc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "ffac_topc_mfc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "ffac_topc_bus0_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const unsigned long topc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) BUS0_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) BUS1_DPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MFC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AUD_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CC_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BUS0_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BUS1_DPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MFC_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AUD_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MUX_SEL_TOPC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MUX_SEL_TOPC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MUX_SEL_TOPC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MUX_SEL_TOPC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DIV_TOPC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DIV_TOPC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DIV_TOPC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX_SEL_TOPC0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MUX_SEL_TOPC0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MUX_SEL_TOPC0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_SEL_TOPC0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MUX_SEL_TOPC0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MUX_SEL_TOPC0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MUX_SEL_TOPC0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_SEL_TOPC0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MUX_SEL_TOPC1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX_SEL_TOPC1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct samsung_div_clock topc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DIV_TOPC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DIV_TOPC1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DIV_TOPC1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DIV_TOPC3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DIV_TOPC3, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DIV_TOPC3, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DIV_TOPC3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DIV_TOPC3, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ENABLE_ACLK_TOPC1, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ENABLE_ACLK_TOPC1, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ENABLE_SCLK_TOPC1, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ENABLE_SCLK_TOPC1, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ENABLE_SCLK_TOPC1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ENABLE_SCLK_TOPC1, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ENABLE_SCLK_TOPC1, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ENABLE_SCLK_TOPC1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ENABLE_SCLK_TOPC1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ENABLE_SCLK_TOPC1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ENABLE_SCLK_TOPC1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BUS0_PLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CC_PLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) BUS1_DPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MFC_PLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) AUD_PLL_CON0, pll1460x_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct samsung_cmu_info topc_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .pll_clks = topc_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .mux_clks = topc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .div_clks = topc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nr_div_clks = ARRAY_SIZE(topc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .gate_clks = topc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .fixed_factor_clks = topc_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .nr_clk_ids = TOPC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .clk_regs = topc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void __init exynos7_clk_topc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) samsung_cmu_register_one(np, &topc_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) exynos7_clk_topc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MUX_SEL_TOP00 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MUX_SEL_TOP01 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MUX_SEL_TOP03 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MUX_SEL_TOP0_PERIC0 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MUX_SEL_TOP0_PERIC1 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MUX_SEL_TOP0_PERIC2 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MUX_SEL_TOP0_PERIC3 0x023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DIV_TOP03 0x060C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DIV_TOP0_PERIC0 0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DIV_TOP0_PERIC1 0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DIV_TOP0_PERIC2 0x0638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DIV_TOP0_PERIC3 0x063C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ENABLE_ACLK_TOP03 0x080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ENABLE_SCLK_TOP0_PERIC0 0x0A30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* List of parent clocks for Muxes in CMU_TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "ffac_top0_bus0_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "ffac_top0_bus1_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "ffac_top0_cc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "ffac_top0_mfc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "mout_top0_mfc_pll_half"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "ioclk_audiocdclk1", "ioclk_spdif_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "mout_top0_bus1_pll_half"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const unsigned long top0_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_SEL_TOP00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX_SEL_TOP01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX_SEL_TOP03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX_SEL_TOP0_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_SEL_TOP0_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX_SEL_TOP0_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX_SEL_TOP0_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DIV_TOP03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DIV_TOP0_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DIV_TOP0_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DIV_TOP0_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DIV_TOP0_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ENABLE_SCLK_TOP0_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ENABLE_SCLK_TOP0_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ENABLE_SCLK_TOP0_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ENABLE_SCLK_TOP0_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX_SEL_TOP00, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX_SEL_TOP00, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX_SEL_TOP00, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX_SEL_TOP00, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX_SEL_TOP00, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MUX_SEL_TOP01, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX_SEL_TOP01, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MUX_SEL_TOP01, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX_SEL_TOP01, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct samsung_div_clock top0_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DIV_TOP03, 12, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DIV_TOP03, 20, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct samsung_cmu_info top0_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mux_clks = top0_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .div_clks = top0_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .nr_div_clks = ARRAY_SIZE(top0_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .gate_clks = top0_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .fixed_factor_clks = top0_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .nr_clk_ids = TOP0_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .clk_regs = top0_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void __init exynos7_clk_top0_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) samsung_cmu_register_one(np, &top0_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) exynos7_clk_top0_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MUX_SEL_TOP10 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MUX_SEL_TOP11 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MUX_SEL_TOP13 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MUX_SEL_TOP1_FSYS0 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MUX_SEL_TOP1_FSYS1 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MUX_SEL_TOP1_FSYS11 0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DIV_TOP13 0x060C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DIV_TOP1_FSYS0 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DIV_TOP1_FSYS1 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DIV_TOP1_FSYS11 0x062C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ENABLE_ACLK_TOP13 0x080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ENABLE_SCLK_TOP1_FSYS0 0x0A24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define ENABLE_SCLK_TOP1_FSYS1 0x0A28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* List of parent clocks for Muxes in CMU_TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "ffac_top1_bus0_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "ffac_top1_bus1_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "ffac_top1_cc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "ffac_top1_mfc_pll_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "mout_top1_mfc_pll_half"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const unsigned long top1_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MUX_SEL_TOP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MUX_SEL_TOP11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MUX_SEL_TOP13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MUX_SEL_TOP1_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MUX_SEL_TOP1_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MUX_SEL_TOP1_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DIV_TOP13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DIV_TOP1_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DIV_TOP1_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DIV_TOP1_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ENABLE_ACLK_TOP13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ENABLE_SCLK_TOP1_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ENABLE_SCLK_TOP1_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ENABLE_SCLK_TOP1_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MUX_SEL_TOP10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MUX_SEL_TOP10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MUX_SEL_TOP10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MUX_SEL_TOP10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MUX_SEL_TOP11, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MUX_SEL_TOP11, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MUX_SEL_TOP11, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MUX_SEL_TOP11, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MUX_SEL_TOP1_FSYS0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MUX_SEL_TOP1_FSYS0, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MUX_SEL_TOP1_FSYS1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MUX_SEL_TOP1_FSYS1, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MUX_SEL_TOP1_FSYS11, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct samsung_div_clock top1_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DIV_TOP13, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DIV_TOP13, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "mout_sclk_ufsunipro20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DIV_TOP1_FSYS1, 16, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DIV_TOP1_FSYS0, 16, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DIV_TOP1_FSYS0, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DIV_TOP1_FSYS11, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DIV_TOP1_FSYS11, 12, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * This clock is required for the CMU_FSYS1 registers access, keep it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * enabled permanently until proper runtime PM support is added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct samsung_cmu_info top1_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .mux_clks = top1_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .div_clks = top1_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .nr_div_clks = ARRAY_SIZE(top1_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .gate_clks = top1_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .fixed_factor_clks = top1_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .nr_clk_ids = TOP1_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .clk_regs = top1_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void __init exynos7_clk_top1_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) samsung_cmu_register_one(np, &top1_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) exynos7_clk_top1_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Register Offset definitions for CMU_CCORE (0x105B0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define MUX_SEL_CCORE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DIV_CCORE 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define ENABLE_ACLK_CCORE0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ENABLE_ACLK_CCORE1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ENABLE_PCLK_CCORE 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * List of parent clocks for Muxes in CMU_CCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const unsigned long ccore_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MUX_SEL_CCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ENABLE_PCLK_CCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MUX_SEL_CCORE, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ENABLE_PCLK_CCORE, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const struct samsung_cmu_info ccore_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .mux_clks = ccore_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .gate_clks = ccore_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .nr_clk_ids = CCORE_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .clk_regs = ccore_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void __init exynos7_clk_ccore_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) samsung_cmu_register_one(np, &ccore_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) exynos7_clk_ccore_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MUX_SEL_PERIC0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ENABLE_PCLK_PERIC0 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ENABLE_SCLK_PERIC0 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* List of parent clocks for Muxes in CMU_PERIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const unsigned long peric0_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MUX_SEL_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ENABLE_SCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MUX_SEL_PERIC0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MUX_SEL_PERIC0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ENABLE_PCLK_PERIC0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ENABLE_PCLK_PERIC0, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ENABLE_PCLK_PERIC0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ENABLE_PCLK_PERIC0, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ENABLE_PCLK_PERIC0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ENABLE_PCLK_PERIC0, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ENABLE_PCLK_PERIC0, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ENABLE_PCLK_PERIC0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ENABLE_PCLK_PERIC0, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ENABLE_PCLK_PERIC0, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ENABLE_SCLK_PERIC0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct samsung_cmu_info peric0_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .mux_clks = peric0_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .gate_clks = peric0_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .nr_clk_ids = PERIC0_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .clk_regs = peric0_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void __init exynos7_clk_peric0_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) samsung_cmu_register_one(np, &peric0_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define MUX_SEL_PERIC10 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define MUX_SEL_PERIC11 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define MUX_SEL_PERIC12 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define ENABLE_PCLK_PERIC1 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define ENABLE_SCLK_PERIC10 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) exynos7_clk_peric0_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* List of parent clocks for Muxes in CMU_PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const unsigned long peric1_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MUX_SEL_PERIC10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MUX_SEL_PERIC11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MUX_SEL_PERIC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ENABLE_PCLK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ENABLE_SCLK_PERIC10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MUX_SEL_PERIC10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MUX_SEL_PERIC11, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MUX_SEL_PERIC11, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MUX_SEL_PERIC11, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ENABLE_PCLK_PERIC1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ENABLE_PCLK_PERIC1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ENABLE_PCLK_PERIC1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ENABLE_PCLK_PERIC1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ENABLE_PCLK_PERIC1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ENABLE_PCLK_PERIC1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ENABLE_PCLK_PERIC1, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ENABLE_PCLK_PERIC1, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ENABLE_PCLK_PERIC1, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ENABLE_PCLK_PERIC1, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ENABLE_PCLK_PERIC1, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ENABLE_PCLK_PERIC1, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ENABLE_PCLK_PERIC1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ENABLE_PCLK_PERIC1, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ENABLE_PCLK_PERIC1, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ENABLE_SCLK_PERIC10, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ENABLE_SCLK_PERIC10, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ENABLE_SCLK_PERIC10, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct samsung_cmu_info peric1_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .mux_clks = peric1_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .gate_clks = peric1_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .nr_clk_ids = PERIC1_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .clk_regs = peric1_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void __init exynos7_clk_peric1_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) samsung_cmu_register_one(np, &peric1_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) exynos7_clk_peric1_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Register Offset definitions for CMU_PERIS (0x10040000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MUX_SEL_PERIS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define ENABLE_PCLK_PERIS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define ENABLE_SCLK_PERIS 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* List of parent clocks for Muxes in CMU_PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const unsigned long peris_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MUX_SEL_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ENABLE_PCLK_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ENABLE_PCLK_PERIS_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ENABLE_SCLK_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ENABLE_SCLK_PERIS_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) MUX(0, "mout_aclk_peris_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ENABLE_PCLK_PERIS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ENABLE_PCLK_PERIS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct samsung_cmu_info peris_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .mux_clks = peris_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .gate_clks = peris_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .nr_clk_ids = PERIS_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .clk_regs = peris_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void __init exynos7_clk_peris_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) samsung_cmu_register_one(np, &peris_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) exynos7_clk_peris_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MUX_SEL_FSYS00 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MUX_SEL_FSYS01 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MUX_SEL_FSYS02 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ENABLE_ACLK_FSYS00 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define ENABLE_ACLK_FSYS01 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define ENABLE_SCLK_FSYS01 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define ENABLE_SCLK_FSYS02 0x0A08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define ENABLE_SCLK_FSYS04 0x0A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * List of parent clocks for Muxes in CMU_FSYS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "phyclk_usbdrd300_udrd30_phyclock" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "phyclk_usbdrd300_udrd30_pipe_pclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* fixed rate clocks used in the FSYS0 block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const unsigned long fsys0_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MUX_SEL_FSYS00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MUX_SEL_FSYS01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MUX_SEL_FSYS02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ENABLE_ACLK_FSYS00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ENABLE_ACLK_FSYS01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ENABLE_SCLK_FSYS01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ENABLE_SCLK_FSYS02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ENABLE_SCLK_FSYS04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MUX_SEL_FSYS00, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MUX_SEL_FSYS01, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MUX_SEL_FSYS01, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MUX_SEL_FSYS02, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MUX_SEL_FSYS02, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ENABLE_ACLK_FSYS00, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ENABLE_ACLK_FSYS00, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "mout_aclk_fsys0_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ENABLE_ACLK_FSYS00, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ENABLE_ACLK_FSYS01, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ENABLE_ACLK_FSYS01, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "mout_sclk_usbdrd300_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ENABLE_SCLK_FSYS01, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ENABLE_SCLK_FSYS01, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) "phyclk_usbdrd300_udrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ENABLE_SCLK_FSYS02, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "phyclk_usbdrd300_udrd30_phyclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "mout_phyclk_usbdrd300_udrd30_phyclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ENABLE_SCLK_FSYS02, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ENABLE_SCLK_FSYS04, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .fixed_clks = fixed_rate_clks_fsys0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .mux_clks = fsys0_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .gate_clks = fsys0_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .nr_clk_ids = FSYS0_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .clk_regs = fsys0_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void __init exynos7_clk_fsys0_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) samsung_cmu_register_one(np, &fsys0_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) exynos7_clk_fsys0_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define MUX_SEL_FSYS10 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define MUX_SEL_FSYS11 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define MUX_SEL_FSYS12 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define DIV_FSYS1 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define ENABLE_ACLK_FSYS1 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define ENABLE_PCLK_FSYS1 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define ENABLE_SCLK_FSYS11 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define ENABLE_SCLK_FSYS12 0x0A08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define ENABLE_SCLK_FSYS13 0x0A0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * List of parent clocks for Muxes in CMU_FSYS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "sclk_phy_fsys1_26m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* fixed rate clocks used in the FSYS1 block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const unsigned long fsys1_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) MUX_SEL_FSYS10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) MUX_SEL_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) MUX_SEL_FSYS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) DIV_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ENABLE_PCLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ENABLE_SCLK_FSYS11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ENABLE_SCLK_FSYS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ENABLE_SCLK_FSYS13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MUX_SEL_FSYS10, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) MUX_SEL_FSYS10, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) MUX_SEL_FSYS11, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) MUX_SEL_FSYS11, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MUX_SEL_FSYS11, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) DIV_FSYS1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "mout_sclk_ufsunipro20_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ENABLE_SCLK_FSYS11, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ENABLE_ACLK_FSYS1, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ENABLE_ACLK_FSYS1, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ENABLE_ACLK_FSYS1, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ENABLE_PCLK_FSYS1, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "mout_phyclk_ufs20_rx1_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ENABLE_SCLK_FSYS12, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "mout_phyclk_ufs20_rx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ENABLE_SCLK_FSYS12, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "mout_phyclk_ufs20_tx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ENABLE_SCLK_FSYS12, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "oscclk_phy_clkout_embedded_combo_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "mout_fsys1_phyclk_sel1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .fixed_clks = fixed_rate_clks_fsys1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .mux_clks = fsys1_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .div_clks = fsys1_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .gate_clks = fsys1_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .nr_clk_ids = FSYS1_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .clk_regs = fsys1_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static void __init exynos7_clk_fsys1_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) samsung_cmu_register_one(np, &fsys1_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) exynos7_clk_fsys1_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define MUX_SEL_MSCL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define DIV_MSCL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define ENABLE_ACLK_MSCL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define ENABLE_PCLK_MSCL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* List of parent clocks for Muxes in CMU_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const unsigned long mscl_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MUX_SEL_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) DIV_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ENABLE_ACLK_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ENABLE_PCLK_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const struct samsung_div_clock mscl_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) DIV_MSCL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ENABLE_ACLK_MSCL, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ENABLE_ACLK_MSCL, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ENABLE_ACLK_MSCL, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ENABLE_ACLK_MSCL, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ENABLE_ACLK_MSCL, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ENABLE_ACLK_MSCL, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ENABLE_ACLK_MSCL, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ENABLE_ACLK_MSCL, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ENABLE_ACLK_MSCL, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ENABLE_ACLK_MSCL, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ENABLE_ACLK_MSCL, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ENABLE_ACLK_MSCL, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ENABLE_ACLK_MSCL, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ENABLE_ACLK_MSCL, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ENABLE_ACLK_MSCL, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ENABLE_ACLK_MSCL, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ENABLE_ACLK_MSCL, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "usermux_aclk_mscl_532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ENABLE_ACLK_MSCL, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ENABLE_PCLK_MSCL, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ENABLE_PCLK_MSCL, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ENABLE_PCLK_MSCL, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ENABLE_PCLK_MSCL, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ENABLE_PCLK_MSCL, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ENABLE_PCLK_MSCL, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ENABLE_PCLK_MSCL, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ENABLE_PCLK_MSCL, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ENABLE_PCLK_MSCL, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ENABLE_PCLK_MSCL, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ENABLE_PCLK_MSCL, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ENABLE_PCLK_MSCL, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct samsung_cmu_info mscl_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .mux_clks = mscl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .div_clks = mscl_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .gate_clks = mscl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .nr_clk_ids = MSCL_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .clk_regs = mscl_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static void __init exynos7_clk_mscl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) samsung_cmu_register_one(np, &mscl_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) exynos7_clk_mscl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Register Offset definitions for CMU_AUD (0x114C0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define MUX_SEL_AUD 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define DIV_AUD0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define DIV_AUD1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define ENABLE_ACLK_AUD 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define ENABLE_PCLK_AUD 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define ENABLE_SCLK_AUD 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * List of parent clocks for Muxes in CMU_AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static const unsigned long aud_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) MUX_SEL_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DIV_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ENABLE_ACLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ENABLE_SCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct samsung_div_clock aud_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ENABLE_SCLK_AUD, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ENABLE_ACLK_AUD, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const struct samsung_cmu_info aud_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .mux_clks = aud_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .div_clks = aud_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .nr_div_clks = ARRAY_SIZE(aud_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .gate_clks = aud_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .nr_clk_ids = AUD_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .clk_regs = aud_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static void __init exynos7_clk_aud_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) samsung_cmu_register_one(np, &aud_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) exynos7_clk_aud_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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