^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chanwoo Choi <cw00.choi@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for Exynos5433 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/exynos5433.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clk-cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Register offset definitions for CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ISP_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUD_PLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISP_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISP_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISP_PLL_FREQ_DET 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AUD_PLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AUD_PLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AUD_PLL_CON2 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AUD_PLL_FREQ_DET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MUX_SEL_TOP0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MUX_SEL_TOP1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MUX_SEL_TOP2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MUX_SEL_TOP3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MUX_SEL_TOP4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_SEL_TOP_MSCL 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUX_SEL_TOP_CAM1 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MUX_SEL_TOP_DISP 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MUX_SEL_TOP_FSYS0 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MUX_SEL_TOP_FSYS1 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MUX_SEL_TOP_PERIC0 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MUX_SEL_TOP_PERIC1 0x023c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MUX_ENABLE_TOP0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MUX_ENABLE_TOP1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MUX_ENABLE_TOP2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MUX_ENABLE_TOP3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MUX_ENABLE_TOP4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MUX_ENABLE_TOP_MSCL 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MUX_ENABLE_TOP_CAM1 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MUX_ENABLE_TOP_DISP 0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MUX_ENABLE_TOP_FSYS0 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MUX_ENABLE_TOP_FSYS1 0x0334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MUX_ENABLE_TOP_PERIC0 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MUX_ENABLE_TOP_PERIC1 0x033c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MUX_STAT_TOP0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MUX_STAT_TOP1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MUX_STAT_TOP2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MUX_STAT_TOP3 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MUX_STAT_TOP4 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MUX_STAT_TOP_MSCL 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MUX_STAT_TOP_CAM1 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MUX_STAT_TOP_FSYS0 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MUX_STAT_TOP_FSYS1 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MUX_STAT_TOP_PERIC0 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MUX_STAT_TOP_PERIC1 0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DIV_TOP0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DIV_TOP1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DIV_TOP2 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DIV_TOP3 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DIV_TOP4 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DIV_TOP_MSCL 0x0618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DIV_TOP_CAM10 0x061c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DIV_TOP_CAM11 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DIV_TOP_FSYS0 0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DIV_TOP_FSYS1 0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DIV_TOP_FSYS2 0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DIV_TOP_PERIC0 0x0638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DIV_TOP_PERIC1 0x063c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DIV_TOP_PERIC2 0x0640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DIV_TOP_PERIC3 0x0644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DIV_TOP_PERIC4 0x0648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DIV_TOP_PLL_FREQ_DET 0x064c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DIV_STAT_TOP0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DIV_STAT_TOP1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DIV_STAT_TOP2 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DIV_STAT_TOP3 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DIV_STAT_TOP4 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DIV_STAT_TOP_MSCL 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DIV_STAT_TOP_CAM10 0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DIV_STAT_TOP_CAM11 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DIV_STAT_TOP_FSYS0 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DIV_STAT_TOP_FSYS1 0x0730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DIV_STAT_TOP_FSYS2 0x0734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DIV_STAT_TOP_PERIC0 0x0738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DIV_STAT_TOP_PERIC1 0x073c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DIV_STAT_TOP_PERIC2 0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DIV_STAT_TOP_PERIC3 0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ENABLE_ACLK_TOP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ENABLE_SCLK_TOP 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ENABLE_SCLK_TOP_MSCL 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ENABLE_SCLK_TOP_CAM1 0x0a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ENABLE_SCLK_TOP_DISP 0x0a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ENABLE_SCLK_TOP_FSYS 0x0a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ENABLE_SCLK_TOP_PERIC 0x0a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ENABLE_IP_TOP 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ENABLE_CMU_TOP 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const unsigned long top_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ISP_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AUD_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ISP_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ISP_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ISP_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AUD_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AUD_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AUD_PLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AUD_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUX_SEL_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_SEL_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX_SEL_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_SEL_TOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX_SEL_TOP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_SEL_TOP_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX_SEL_TOP_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_SEL_TOP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_SEL_TOP_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_SEL_TOP_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX_SEL_TOP_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_SEL_TOP_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUX_ENABLE_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_ENABLE_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MUX_ENABLE_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_ENABLE_TOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_ENABLE_TOP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_ENABLE_TOP_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX_ENABLE_TOP_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_ENABLE_TOP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_ENABLE_TOP_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MUX_ENABLE_TOP_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_ENABLE_TOP_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_ENABLE_TOP_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DIV_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DIV_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DIV_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DIV_TOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DIV_TOP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DIV_TOP_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DIV_TOP_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DIV_TOP_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DIV_TOP_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DIV_TOP_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DIV_TOP_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DIV_TOP_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DIV_TOP_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DIV_TOP_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DIV_TOP_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DIV_TOP_PERIC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DIV_TOP_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ENABLE_ACLK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ENABLE_SCLK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ENABLE_SCLK_TOP_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ENABLE_SCLK_TOP_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ENABLE_SCLK_TOP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ENABLE_SCLK_TOP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ENABLE_SCLK_TOP_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ENABLE_IP_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ENABLE_CMU_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ENABLE_CMU_TOP_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct samsung_clk_reg_dump top_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* force all aclk clocks enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { ENABLE_ACLK_TOP, 0x67ecffed },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* force all sclk_uart clocks enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { ENABLE_SCLK_TOP_PERIC, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { ISP_PLL_CON0, 0x85cc0502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { AUD_PLL_CON0, 0x84830202 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "mout_mfc_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "mout_mphy_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "mout_bus_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "mout_mphy_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "mout_mphy_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "mout_mphy_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "oscclk", "ioclk_spdif_extclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "mout_aud_pll_user_t",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "mout_aud_pll_user_t",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Xi2s1SDI input clock for SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* XspiCLK[4:0] input clock for SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Xi2s1SCLK input clock for I2S1_BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct samsung_mux_clock top_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* MUX_SEL_TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* MUX_SEL_TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MUX_SEL_TOP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX_SEL_TOP1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX_SEL_TOP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* MUX_SEL_TOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* MUX_SEL_TOP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* MUX_SEL_TOP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* MUX_SEL_TOP_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX_SEL_TOP_MSCL, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX_SEL_TOP_MSCL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MUX_SEL_TOP_MSCL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* MUX_SEL_TOP_CAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* MUX_SEL_TOP_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MUX_SEL_TOP_FSYS0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MUX_SEL_TOP_FSYS0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MUX_SEL_TOP_FSYS0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MUX_SEL_TOP_FSYS0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MUX_SEL_TOP_FSYS0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MUX_SEL_TOP_FSYS0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MUX_SEL_TOP_FSYS0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MUX_SEL_TOP_FSYS0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* MUX_SEL_TOP_FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MUX_SEL_TOP_FSYS1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* MUX_SEL_TOP_PERIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MUX_SEL_TOP_PERIC0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MUX_SEL_TOP_PERIC0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MUX_SEL_TOP_PERIC0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MUX_SEL_TOP_PERIC0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MUX_SEL_TOP_PERIC0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MUX_SEL_TOP_PERIC0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MUX_SEL_TOP_PERIC0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MUX_SEL_TOP_PERIC0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* MUX_SEL_TOP_PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MUX_SEL_TOP_PERIC1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MUX_SEL_TOP_PERIC1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MUX_SEL_TOP_PERIC1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MUX_SEL_TOP_PERIC1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* MUX_SEL_TOP_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct samsung_div_clock top_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* DIV_TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DIV_TOP0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DIV_TOP0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DIV_TOP0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DIV_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DIV_TOP0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DIV_TOP0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "mout_aclk_isp_400", DIV_TOP0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* DIV_TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DIV_TOP1, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DIV_TOP1, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DIV_TOP1, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DIV_TOP1, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DIV_TOP1, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DIV_TOP1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* DIV_TOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DIV_TOP2, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DIV_TOP2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* DIV_TOP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "mout_bus_pll_user", DIV_TOP3, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "mout_bus_pll_user", DIV_TOP3, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "mout_bus_pll_user", DIV_TOP3, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "mout_bus_pll_user", DIV_TOP3, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "mout_bus_pll_user", DIV_TOP3, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* DIV_TOP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DIV_TOP4, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DIV_TOP4, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DIV_TOP4, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* DIV_TOP_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DIV_TOP_MSCL, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* DIV_TOP_CAM10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DIV_TOP_CAM10, 24, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* DIV_TOP_CAM11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* DIV_TOP_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DIV_TOP_FSYS0, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DIV_TOP_FSYS0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* DIV_TOP_FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DIV_TOP_FSYS1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DIV_TOP_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* DIV_TOP_FSYS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DIV_TOP_FSYS2, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DIV_TOP_FSYS2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* DIV_TOP_PERIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DIV_TOP_PERIC0, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DIV_TOP_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DIV_TOP_PERIC0, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DIV_TOP_PERIC0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* DIV_TOP_PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) DIV_TOP_PERIC1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DIV_TOP_PERIC1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* DIV_TOP_PERIC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) DIV_TOP_PERIC2, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DIV_TOP_PERIC2, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DIV_TOP_PERIC2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* DIV_TOP_PERIC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DIV_TOP_PERIC3, 16, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DIV_TOP_PERIC3, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DIV_TOP_PERIC3, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DIV_TOP_PERIC3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* DIV_TOP_PERIC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DIV_TOP_PERIC4, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DIV_TOP_PERIC4, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DIV_TOP_PERIC4, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DIV_TOP_PERIC4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct samsung_gate_clock top_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* ENABLE_ACLK_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ENABLE_ACLK_TOP, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ENABLE_ACLK_TOP, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ENABLE_ACLK_TOP, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ENABLE_ACLK_TOP, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ENABLE_ACLK_TOP, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ENABLE_ACLK_TOP, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ENABLE_ACLK_TOP, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ENABLE_ACLK_TOP, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ENABLE_ACLK_TOP, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ENABLE_ACLK_TOP, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ENABLE_ACLK_TOP, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ENABLE_ACLK_TOP, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ENABLE_ACLK_TOP, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ENABLE_ACLK_TOP, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ENABLE_ACLK_TOP, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ENABLE_ACLK_TOP, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ENABLE_ACLK_TOP, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ENABLE_ACLK_TOP, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ENABLE_ACLK_TOP, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ENABLE_ACLK_TOP, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ENABLE_ACLK_TOP, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ENABLE_ACLK_TOP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* ENABLE_SCLK_TOP_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* ENABLE_SCLK_TOP_CAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* ENABLE_SCLK_TOP_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* ENABLE_SCLK_TOP_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* ENABLE_SCLK_TOP_PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* MUX_ENABLE_TOP_PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* AUD_PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct samsung_pll_clock top_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct samsung_cmu_info top_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .pll_clks = top_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .mux_clks = top_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .div_clks = top_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .nr_div_clks = ARRAY_SIZE(top_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .gate_clks = top_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .fixed_clks = top_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .fixed_factor_clks = top_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .nr_clk_ids = TOP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .clk_regs = top_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .suspend_regs = top_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void __init exynos5433_cmu_top_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) samsung_cmu_register_one(np, &top_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) exynos5433_cmu_top_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * Register offset definitions for CMU_CPIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define MPHY_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MPHY_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MPHY_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MPHY_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define MUX_SEL_CPIF0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DIV_CPIF 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define ENABLE_SCLK_CPIF 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const unsigned long cpif_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MPHY_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MPHY_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MPHY_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) MPHY_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MUX_SEL_CPIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) DIV_CPIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ENABLE_SCLK_CPIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* force all sclk clocks enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { ENABLE_SCLK_CPIF, 0x3ff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) { MPHY_PLL_CON0, 0x81c70601 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* MUX_SEL_CPIF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct samsung_div_clock cpif_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* DIV_CPIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* ENABLE_SCLK_CPIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ENABLE_SCLK_CPIF, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static const struct samsung_cmu_info cpif_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .pll_clks = cpif_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .mux_clks = cpif_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .div_clks = cpif_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .gate_clks = cpif_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .nr_clk_ids = CPIF_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .clk_regs = cpif_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .suspend_regs = cpif_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void __init exynos5433_cmu_cpif_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) samsung_cmu_register_one(np, &cpif_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) exynos5433_cmu_cpif_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * Register offset definitions for CMU_MIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MEM0_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define MEM1_PLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define BUS_PLL_LOCK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MFC_PLL_LOCK 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MEM0_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MEM0_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define MEM0_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define MEM1_PLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define MEM1_PLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define MEM1_PLL_FREQ_DET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define BUS_PLL_CON0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define BUS_PLL_CON1 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define BUS_PLL_FREQ_DET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define MFC_PLL_CON0 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define MFC_PLL_CON1 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define MFC_PLL_FREQ_DET 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define MUX_SEL_MIF0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define MUX_SEL_MIF1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define MUX_SEL_MIF2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define MUX_SEL_MIF3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define MUX_SEL_MIF4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define MUX_SEL_MIF5 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define MUX_SEL_MIF6 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define MUX_SEL_MIF7 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define MUX_ENABLE_MIF0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define MUX_ENABLE_MIF1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define MUX_ENABLE_MIF2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define MUX_ENABLE_MIF3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define MUX_ENABLE_MIF4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define MUX_ENABLE_MIF5 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define MUX_ENABLE_MIF6 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define MUX_ENABLE_MIF7 0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define MUX_STAT_MIF0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define MUX_STAT_MIF1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define MUX_STAT_MIF2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define MUX_STAT_MIF3 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define MUX_STAT_MIF4 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define MUX_STAT_MIF5 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define MUX_STAT_MIF6 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define MUX_STAT_MIF7 0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define DIV_MIF1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define DIV_MIF2 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define DIV_MIF3 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DIV_MIF4 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define DIV_MIF5 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define DIV_MIF_PLL_FREQ_DET 0x0618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define DIV_STAT_MIF1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define DIV_STAT_MIF2 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define DIV_STAT_MIF3 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define DIV_STAT_MIF4 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define DIV_STAT_MIF5 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define ENABLE_ACLK_MIF0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define ENABLE_ACLK_MIF1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define ENABLE_ACLK_MIF2 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define ENABLE_ACLK_MIF3 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define ENABLE_PCLK_MIF 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define ENABLE_SCLK_MIF 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define ENABLE_IP_MIF0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define ENABLE_IP_MIF1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define ENABLE_IP_MIF2 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define ENABLE_IP_MIF3 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define CLKOUT_CMU_MIF 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define DREX_FREQ_CTRL0 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define DREX_FREQ_CTRL1 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define PAUSE 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define DDRPHY_LOCK_CTRL 0x100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned long mif_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MEM0_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MEM1_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) BUS_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MFC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MEM0_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MEM0_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) MEM0_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MEM1_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MEM1_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) MEM1_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) BUS_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) BUS_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) BUS_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) MFC_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) MFC_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) MFC_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MUX_SEL_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) MUX_SEL_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) MUX_SEL_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) MUX_SEL_MIF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) MUX_SEL_MIF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) MUX_SEL_MIF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) MUX_SEL_MIF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) MUX_SEL_MIF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) MUX_ENABLE_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) MUX_ENABLE_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) MUX_ENABLE_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) MUX_ENABLE_MIF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MUX_ENABLE_MIF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) MUX_ENABLE_MIF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MUX_ENABLE_MIF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MUX_ENABLE_MIF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) DIV_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DIV_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) DIV_MIF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) DIV_MIF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) DIV_MIF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) DIV_MIF_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ENABLE_ACLK_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ENABLE_ACLK_MIF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ENABLE_PCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ENABLE_PCLK_MIF_SECURE_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ENABLE_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ENABLE_IP_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ENABLE_IP_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ENABLE_IP_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ENABLE_IP_MIF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ENABLE_IP_MIF_SECURE_DREX0_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ENABLE_IP_MIF_SECURE_DREX1_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ENABLE_IP_MIF_SECURE_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) CLKOUT_CMU_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) CLKOUT_CMU_MIF_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) DREX_FREQ_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) DREX_FREQ_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) DDRPHY_LOCK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "mout_bus_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "mout_mfc_pll_div2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* MUX_SEL_MIF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) MUX_SEL_MIF0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) MUX_SEL_MIF0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) MUX_SEL_MIF0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) MUX_SEL_MIF0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* MUX_SEL_MIF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) MUX_SEL_MIF1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) MUX_SEL_MIF1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MUX_SEL_MIF1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MUX_SEL_MIF1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) MUX_SEL_MIF1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) MUX_SEL_MIF1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* MUX_SEL_MIF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* MUX_SEL_MIF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* MUX_SEL_MIF4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* MUX_SEL_MIF5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MUX_SEL_MIF5, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MUX_SEL_MIF5, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MUX_SEL_MIF5, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* MUX_SEL_MIF6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) MUX_SEL_MIF6, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MUX_SEL_MIF6, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) MUX_SEL_MIF6, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* MUX_SEL_MIF7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) MUX_SEL_MIF7, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) MUX_SEL_MIF7, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) MUX_SEL_MIF7, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct samsung_div_clock mif_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* DIV_MIF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) DIV_MIF1, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* DIV_MIF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) DIV_MIF2, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) DIV_MIF2, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) DIV_MIF2, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) DIV_MIF2, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) DIV_MIF2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* DIV_MIF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) DIV_MIF3, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) DIV_MIF3, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) DIV_MIF3, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* DIV_MIF4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) DIV_MIF4, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) DIV_MIF4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DIV_MIF4, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* DIV_MIF5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* ENABLE_ACLK_MIF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* ENABLE_ACLK_MIF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "div_aclk_mif_200", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "div_aclk_drex1", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) "div_aclk_drex0", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) "div_aclk_drex1", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "div_aclk_drex1", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "div_aclk_drex1", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) "div_aclk_drex0", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) "div_aclk_drex0", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) "div_aclk_mif_133", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "div_aclk_drex0", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* ENABLE_ACLK_MIF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) "div_aclk_mif_400", ENABLE_ACLK_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) "div_aclk_mif_200", ENABLE_ACLK_MIF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* ENABLE_ACLK_MIF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ENABLE_ACLK_MIF3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ENABLE_ACLK_MIF3, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ENABLE_ACLK_MIF3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* ENABLE_PCLK_MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ENABLE_PCLK_MIF, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ENABLE_PCLK_MIF, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ENABLE_PCLK_MIF, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ENABLE_PCLK_MIF, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ENABLE_PCLK_MIF, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ENABLE_PCLK_MIF, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* ENABLE_PCLK_MIF_SECURE_RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* ENABLE_SCLK_MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ENABLE_SCLK_MIF, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static const struct samsung_cmu_info mif_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .pll_clks = mif_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .mux_clks = mif_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .div_clks = mif_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .nr_div_clks = ARRAY_SIZE(mif_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .gate_clks = mif_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .fixed_factor_clks = mif_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .nr_clk_ids = MIF_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .clk_regs = mif_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static void __init exynos5433_cmu_mif_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) samsung_cmu_register_one(np, &mif_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) exynos5433_cmu_mif_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * Register offset definitions for CMU_PERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define DIV_PERIC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define DIV_STAT_PERIC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define ENABLE_ACLK_PERIC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define ENABLE_PCLK_PERIC0 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define ENABLE_PCLK_PERIC1 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define ENABLE_SCLK_PERIC 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define ENABLE_IP_PERIC0 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define ENABLE_IP_PERIC1 0x0B04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define ENABLE_IP_PERIC2 0x0B08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static const unsigned long peric_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) DIV_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ENABLE_ACLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ENABLE_PCLK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ENABLE_IP_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ENABLE_IP_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ENABLE_IP_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) { ENABLE_PCLK_PERIC0, 0xe00ff000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* sclk: uart2-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) { ENABLE_SCLK_PERIC, 0x7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const struct samsung_div_clock peric_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* DIV_PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* ENABLE_ACLK_PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* ENABLE_PCLK_PERIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) 31, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) 28, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) 26, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) 25, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) 23, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) 22, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) 21, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ENABLE_PCLK_PERIC0, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) 14, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) 13, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* ENABLE_PCLK_PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* ENABLE_SCLK_PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) 19, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) 18, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ENABLE_SCLK_PERIC, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ENABLE_SCLK_PERIC, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) ENABLE_SCLK_PERIC, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ENABLE_SCLK_PERIC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static const struct samsung_cmu_info peric_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .div_clks = peric_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .nr_div_clks = ARRAY_SIZE(peric_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .gate_clks = peric_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .nr_clk_ids = PERIC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .clk_regs = peric_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .suspend_regs = peric_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static void __init exynos5433_cmu_peric_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) samsung_cmu_register_one(np, &peric_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) exynos5433_cmu_peric_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * Register offset definitions for CMU_PERIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define ENABLE_ACLK_PERIS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define ENABLE_PCLK_PERIS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define ENABLE_SCLK_PERIS 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define ENABLE_IP_PERIS0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define ENABLE_IP_PERIS1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static const unsigned long peris_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ENABLE_ACLK_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ENABLE_PCLK_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) ENABLE_PCLK_PERIS_SECURE_TZPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ENABLE_PCLK_PERIS_SECURE_TOPRTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ENABLE_SCLK_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ENABLE_SCLK_PERIS_SECURE_SECKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ENABLE_SCLK_PERIS_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ENABLE_SCLK_PERIS_SECURE_TOPRTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ENABLE_SCLK_PERIS_SECURE_OTP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ENABLE_IP_PERIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ENABLE_IP_PERIS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ENABLE_IP_PERIS_SECURE_TZPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ENABLE_IP_PERIS_SECURE_SECKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ENABLE_IP_PERIS_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ENABLE_IP_PERIS_SECURE_TOPRTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ENABLE_IP_PERIS_SECURE_OTP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* ENABLE_ACLK_PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* ENABLE_PCLK_PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* ENABLE_PCLK_PERIS_SECURE_TZPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "aclk_peris_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* ENABLE_SCLK_PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ENABLE_SCLK_PERIS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ENABLE_SCLK_PERIS, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ENABLE_SCLK_PERIS, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const struct samsung_cmu_info peris_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .gate_clks = peris_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .nr_clk_ids = PERIS_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .clk_regs = peris_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static void __init exynos5433_cmu_peris_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) samsung_cmu_register_one(np, &peris_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) exynos5433_cmu_peris_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * Register offset definitions for CMU_FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define MUX_SEL_FSYS0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define MUX_SEL_FSYS1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define MUX_SEL_FSYS2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define MUX_SEL_FSYS3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define MUX_SEL_FSYS4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define MUX_ENABLE_FSYS0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define MUX_ENABLE_FSYS1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define MUX_ENABLE_FSYS2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define MUX_ENABLE_FSYS3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define MUX_ENABLE_FSYS4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define MUX_STAT_FSYS0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define MUX_STAT_FSYS1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define MUX_STAT_FSYS2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define MUX_STAT_FSYS3 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define MUX_STAT_FSYS4 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define MUX_IGNORE_FSYS2 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define MUX_IGNORE_FSYS3 0x050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define ENABLE_ACLK_FSYS0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define ENABLE_ACLK_FSYS1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define ENABLE_PCLK_FSYS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define ENABLE_SCLK_FSYS 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define ENABLE_IP_FSYS0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define ENABLE_IP_FSYS1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) PNAME(mout_sclk_mphy_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) = { "mout_sclk_ufs_mphy_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "mout_phyclk_lli_mphy_to_ufs_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static const unsigned long fsys_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) MUX_SEL_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) MUX_SEL_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) MUX_SEL_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) MUX_SEL_FSYS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) MUX_SEL_FSYS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) MUX_ENABLE_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) MUX_ENABLE_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) MUX_ENABLE_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) MUX_ENABLE_FSYS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) MUX_ENABLE_FSYS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) MUX_IGNORE_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) MUX_IGNORE_FSYS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ENABLE_ACLK_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ENABLE_PCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ENABLE_IP_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ENABLE_IP_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) { MUX_SEL_FSYS0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) { MUX_SEL_FSYS1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) { MUX_SEL_FSYS2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) { MUX_SEL_FSYS3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) { MUX_SEL_FSYS4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* PHY clocks from USBDRD30_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) 0, 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /* PHY clocks from USBHOST30_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) 0, 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* PHY clocks from USBHOST20_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* PHY clocks from UFS_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) NULL, 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) NULL, 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) NULL, 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) NULL, 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* PHY clocks from LLI_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) NULL, 0, 26000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /* MUX_SEL_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* MUX_SEL_FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* MUX_SEL_FSYS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) MUX_SEL_FSYS2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) "mout_phyclk_usbhost30_uhost30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) mout_phyclk_usbhost30_uhost30_phyclock_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) MUX_SEL_FSYS2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) "mout_phyclk_usbhost20_phy_hsic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) mout_phyclk_usbhost20_phy_hsic1_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) MUX_SEL_FSYS2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) "mout_phyclk_usbhost20_phy_clk48mohci_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) mout_phyclk_usbhost20_phy_clk48mohci_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) MUX_SEL_FSYS2, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) "mout_phyclk_usbhost20_phy_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) mout_phyclk_usbhost20_phy_phyclock_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) MUX_SEL_FSYS2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) "mout_phyclk_usbhost20_phy_freeclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) mout_phyclk_usbhost20_phy_freeclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) MUX_SEL_FSYS2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) MUX_SEL_FSYS2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) "mout_phyclk_usbdrd30_udrd30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) MUX_SEL_FSYS2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* MUX_SEL_FSYS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) "mout_phyclk_ufs_rx1_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) mout_phyclk_ufs_rx1_symbol_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) MUX_SEL_FSYS3, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) "mout_phyclk_ufs_rx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) mout_phyclk_ufs_rx0_symbol_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) MUX_SEL_FSYS3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) "mout_phyclk_ufs_tx1_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) mout_phyclk_ufs_tx1_symbol_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) MUX_SEL_FSYS3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) "mout_phyclk_ufs_tx0_symbol_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) mout_phyclk_ufs_tx0_symbol_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) MUX_SEL_FSYS3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) "mout_phyclk_lli_mphy_to_ufs_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) mout_phyclk_lli_mphy_to_ufs_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) MUX_SEL_FSYS3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* MUX_SEL_FSYS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) MUX_SEL_FSYS4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* ENABLE_ACLK_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /* ENABLE_ACLK_FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* ENABLE_PCLK_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ENABLE_PCLK_FSYS, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* ENABLE_SCLK_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ENABLE_SCLK_FSYS, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "phyclk_usbhost30_uhost30_pipe_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ENABLE_SCLK_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) "phyclk_usbhost30_uhost30_phyclock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) "mout_phyclk_usbhost30_uhost30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) ENABLE_SCLK_FSYS, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) "phyclk_usbhost20_phy_clk48mohci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) "mout_phyclk_usbhost20_phy_clk48mohci_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ENABLE_SCLK_FSYS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) "phyclk_usbhost20_phy_phyclock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) "mout_phyclk_usbhost20_phy_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ENABLE_SCLK_FSYS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) "phyclk_usbhost20_phy_freeclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) "mout_phyclk_usbhost20_phy_freeclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ENABLE_SCLK_FSYS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) "phyclk_usbdrd30_udrd30_pipe_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ENABLE_SCLK_FSYS, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) "phyclk_usbdrd30_udrd30_phyclock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) "mout_phyclk_usbdrd30_udrd30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ENABLE_SCLK_FSYS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ENABLE_SCLK_FSYS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ENABLE_SCLK_FSYS, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ENABLE_SCLK_FSYS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) ENABLE_SCLK_FSYS, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /* ENABLE_IP_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static const struct samsung_cmu_info fsys_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .mux_clks = fsys_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .gate_clks = fsys_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .fixed_clks = fsys_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .nr_clk_ids = FSYS_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .clk_regs = fsys_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .suspend_regs = fsys_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .clk_name = "aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * Register offset definitions for CMU_G2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) #define MUX_SEL_G2D0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #define MUX_SEL_ENABLE_G2D0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define MUX_SEL_STAT_G2D0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define DIV_G2D 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #define DIV_STAT_G2D 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define DIV_ENABLE_ACLK_G2D 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define DIV_ENABLE_PCLK_G2D 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define DIV_ENABLE_IP_G2D0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #define DIV_ENABLE_IP_G2D1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static const unsigned long g2d_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) MUX_SEL_G2D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) MUX_SEL_ENABLE_G2D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) DIV_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) DIV_ENABLE_ACLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) DIV_ENABLE_PCLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) DIV_ENABLE_IP_G2D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) DIV_ENABLE_IP_G2D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) { MUX_SEL_G2D0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /* MUX_SEL_G2D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static const struct samsung_div_clock g2d_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) /* DIV_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) DIV_G2D, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* DIV_ENABLE_ACLK_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) DIV_ENABLE_ACLK_G2D, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) DIV_ENABLE_ACLK_G2D, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) DIV_ENABLE_ACLK_G2D, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) DIV_ENABLE_ACLK_G2D, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) DIV_ENABLE_ACLK_G2D, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) DIV_ENABLE_ACLK_G2D, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) DIV_ENABLE_ACLK_G2D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* DIV_ENABLE_PCLK_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) DIV_ENABLE_PCLK_G2D, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) DIV_ENABLE_PCLK_G2D, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) DIV_ENABLE_PCLK_G2D, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) DIV_ENABLE_PCLK_G2D, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) DIV_ENABLE_PCLK_G2D, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) static const struct samsung_cmu_info g2d_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .mux_clks = g2d_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .div_clks = g2d_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .gate_clks = g2d_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .nr_clk_ids = G2D_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .clk_regs = g2d_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .suspend_regs = g2d_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .clk_name = "aclk_g2d_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) * Register offset definitions for CMU_DISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) #define DISP_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #define DISP_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) #define DISP_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #define DISP_PLL_FREQ_DET 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #define MUX_SEL_DISP0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define MUX_SEL_DISP1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define MUX_SEL_DISP2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #define MUX_SEL_DISP3 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define MUX_SEL_DISP4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define MUX_ENABLE_DISP0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define MUX_ENABLE_DISP1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define MUX_ENABLE_DISP2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) #define MUX_ENABLE_DISP3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #define MUX_ENABLE_DISP4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define MUX_STAT_DISP0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #define MUX_STAT_DISP1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define MUX_STAT_DISP2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #define MUX_STAT_DISP3 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) #define MUX_STAT_DISP4 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define MUX_IGNORE_DISP2 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define DIV_DISP 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) #define DIV_DISP_PLL_FREQ_DET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #define DIV_STAT_DISP 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #define ENABLE_ACLK_DISP0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #define ENABLE_ACLK_DISP1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define ENABLE_PCLK_DISP 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define ENABLE_SCLK_DISP 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define ENABLE_IP_DISP0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) #define ENABLE_IP_DISP1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) #define CLKOUT_CMU_DISP 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static const unsigned long disp_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) DISP_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) DISP_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) DISP_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) DISP_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) MUX_SEL_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) MUX_SEL_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) MUX_SEL_DISP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) MUX_SEL_DISP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) MUX_ENABLE_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) MUX_ENABLE_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) MUX_ENABLE_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) MUX_ENABLE_DISP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) MUX_ENABLE_DISP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) MUX_IGNORE_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) DIV_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) DIV_DISP_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ENABLE_ACLK_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ENABLE_ACLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ENABLE_PCLK_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) ENABLE_SCLK_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ENABLE_IP_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ENABLE_IP_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) CLKOUT_CMU_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) CLKOUT_CMU_DISP_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) /* PLL has to be enabled for suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) { DISP_PLL_CON0, 0x85f40502 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* ignore status of external PHY muxes during suspend to avoid hangs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) { MUX_IGNORE_DISP2, 0x00111111 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) { MUX_SEL_DISP0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) { MUX_SEL_DISP1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) { MUX_SEL_DISP2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) { MUX_SEL_DISP3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) { MUX_SEL_DISP4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) "sclk_decon_tv_eclk_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) "sclk_decon_vclk_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) "sclk_decon_eclk_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) "sclk_decon_tv_vclk_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) "phyclk_mipidphy1_bitclkdiv8_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) "phyclk_mipidphy1_rxclkesc0_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) "phyclk_mipidphy0_bitclkdiv8_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) "phyclk_mipidphy0_rxclkesc0_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) "phyclk_hdmiphy_tmds_clko_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) "phyclk_hdmiphy_pixel_clko_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) "mout_sclk_dsim0_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) "mout_sclk_decon_tv_eclk_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) "mout_sclk_decon_vclk_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) "mout_sclk_decon_eclk_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) "mout_sclk_dsim1_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) "mout_phyclk_hdmiphy_pixel_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) "mout_sclk_decon_tv_vclk_b_disp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) "mout_sclk_decon_tv_vclk_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) * and sclk_decon_{vclk|tv_vclk}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* PHY clocks from MIPI_DPHY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /* PHY clocks from MIPI_DPHY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) NULL, 0, 188000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) /* PHY clocks from HDMI_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) NULL, 0, 300000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) NULL, 0, 166000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* MUX_SEL_DISP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* MUX_SEL_DISP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) MUX_SEL_DISP1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /* MUX_SEL_DISP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) "mout_phyclk_mipidphy1_bitclkdiv8_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) "mout_phyclk_mipidphy1_rxclkesc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) "mout_phyclk_mipidphy0_bitclkdiv8_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) "mout_phyclk_mipidphy0_rxclkesc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) "mout_phyclk_hdmiphy_tmds_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) "mout_phyclk_hdmiphy_pixel_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) /* MUX_SEL_DISP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) MUX_SEL_DISP3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) /* MUX_SEL_DISP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) "mout_sclk_decon_tv_vclk_c_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) "mout_sclk_decon_tv_vclk_b_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) "mout_sclk_decon_tv_vclk_a_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static const struct samsung_div_clock disp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* DIV_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) DIV_DISP, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) DIV_DISP, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) /* ENABLE_ACLK_DISP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) ENABLE_ACLK_DISP0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) ENABLE_ACLK_DISP0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* ENABLE_ACLK_DISP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ENABLE_ACLK_DISP1, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) ENABLE_ACLK_DISP1, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) "div_pclk_disp", ENABLE_ACLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) "div_pclk_disp", ENABLE_ACLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) "div_pclk_disp", ENABLE_ACLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) ENABLE_ACLK_DISP1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ENABLE_ACLK_DISP1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) /* ENABLE_PCLK_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) ENABLE_PCLK_DISP, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) ENABLE_PCLK_DISP, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) ENABLE_PCLK_DISP, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) ENABLE_PCLK_DISP, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) ENABLE_PCLK_DISP, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ENABLE_PCLK_DISP, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) ENABLE_PCLK_DISP, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) ENABLE_PCLK_DISP, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) ENABLE_PCLK_DISP, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) ENABLE_PCLK_DISP, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) ENABLE_PCLK_DISP, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) ENABLE_PCLK_DISP, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) ENABLE_PCLK_DISP, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ENABLE_PCLK_DISP, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ENABLE_PCLK_DISP, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) ENABLE_PCLK_DISP, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) ENABLE_PCLK_DISP, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ENABLE_PCLK_DISP, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) ENABLE_PCLK_DISP, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) ENABLE_PCLK_DISP, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) ENABLE_PCLK_DISP, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /* ENABLE_SCLK_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) "mout_phyclk_mipidphy1_bitclkdiv8_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) ENABLE_SCLK_DISP, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) "mout_phyclk_mipidphy1_rxclkesc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) ENABLE_SCLK_DISP, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ENABLE_SCLK_DISP, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) "div_sclk_decon_tv_vclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) ENABLE_SCLK_DISP, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) "mout_phyclk_mipidphy0_bitclkdiv8_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) ENABLE_SCLK_DISP, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) "mout_phyclk_mipidphy0_rxclkesc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) ENABLE_SCLK_DISP, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) "mout_phyclk_hdmiphy_tmds_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) ENABLE_SCLK_DISP, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) ENABLE_SCLK_DISP, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) ENABLE_SCLK_DISP, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) ENABLE_SCLK_DISP, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) "div_sclk_decon_tv_eclk_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) ENABLE_SCLK_DISP, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static const struct samsung_cmu_info disp_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .pll_clks = disp_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .mux_clks = disp_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .div_clks = disp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .nr_div_clks = ARRAY_SIZE(disp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .gate_clks = disp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .fixed_clks = disp_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) .fixed_factor_clks = disp_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .nr_clk_ids = DISP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .clk_regs = disp_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .suspend_regs = disp_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .clk_name = "aclk_disp_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) * Register offset definitions for CMU_AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define MUX_SEL_AUD0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) #define MUX_SEL_AUD1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) #define MUX_ENABLE_AUD0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) #define MUX_ENABLE_AUD1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define MUX_STAT_AUD0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #define DIV_AUD0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) #define DIV_AUD1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) #define DIV_STAT_AUD0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) #define DIV_STAT_AUD1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) #define ENABLE_ACLK_AUD 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) #define ENABLE_PCLK_AUD 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) #define ENABLE_SCLK_AUD0 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) #define ENABLE_SCLK_AUD1 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) #define ENABLE_IP_AUD0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) #define ENABLE_IP_AUD1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) static const unsigned long aud_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) MUX_SEL_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) MUX_SEL_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) MUX_ENABLE_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) MUX_ENABLE_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) DIV_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) ENABLE_ACLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ENABLE_SCLK_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) ENABLE_SCLK_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) ENABLE_IP_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ENABLE_IP_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) { MUX_SEL_AUD0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) { MUX_SEL_AUD1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /* MUX_SEL_AUD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /* MUX_SEL_AUD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) MUX_SEL_AUD1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) MUX_SEL_AUD1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) static const struct samsung_div_clock aud_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) /* DIV_AUD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) /* DIV_AUD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) "mout_aud_pll_user", DIV_AUD1, 16, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) DIV_AUD1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) DIV_AUD1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) DIV_AUD1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) /* ENABLE_ACLK_AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) ENABLE_ACLK_AUD, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) ENABLE_ACLK_AUD, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) ENABLE_ACLK_AUD, 0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) ENABLE_ACLK_AUD, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) ENABLE_ACLK_AUD, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) /* ENABLE_PCLK_AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) ENABLE_PCLK_AUD, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ENABLE_PCLK_AUD, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) ENABLE_PCLK_AUD, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) ENABLE_PCLK_AUD, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ENABLE_PCLK_AUD, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) ENABLE_PCLK_AUD, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) /* ENABLE_SCLK_AUD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) ENABLE_SCLK_AUD0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /* ENABLE_SCLK_AUD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) ENABLE_SCLK_AUD1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) ENABLE_SCLK_AUD1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) ENABLE_SCLK_AUD1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) ENABLE_SCLK_AUD1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static const struct samsung_cmu_info aud_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .mux_clks = aud_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .div_clks = aud_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .nr_div_clks = ARRAY_SIZE(aud_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .gate_clks = aud_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) .fixed_clks = aud_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .nr_clk_ids = AUD_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .clk_regs = aud_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .suspend_regs = aud_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) .clk_name = "fout_aud_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) * Register offset definitions for CMU_BUS{0|1|2}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) #define DIV_BUS 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #define DIV_STAT_BUS 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) #define ENABLE_ACLK_BUS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #define ENABLE_PCLK_BUS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #define ENABLE_IP_BUS0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) #define ENABLE_IP_BUS1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define CMU_BUS_COMMON_CLK_REGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) DIV_BUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) ENABLE_ACLK_BUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) ENABLE_PCLK_BUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) ENABLE_IP_BUS0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) ENABLE_IP_BUS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) static const unsigned long bus01_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) CMU_BUS_COMMON_CLK_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) static const unsigned long bus2_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) MUX_SEL_BUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) MUX_ENABLE_BUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) CMU_BUS_COMMON_CLK_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static const struct samsung_div_clock bus0_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) /* DIV_BUS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) DIV_BUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) /* CMU_BUS0 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* ENABLE_ACLK_BUS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /* ENABLE_PCLK_BUS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) ENABLE_PCLK_BUS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) /* CMU_BUS1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) static const struct samsung_div_clock bus1_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) /* DIV_BUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) DIV_BUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) /* ENABLE_ACLK_BUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) /* ENABLE_PCLK_BUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) ENABLE_PCLK_BUS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* CMU_BUS2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) /* MUX_SEL_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static const struct samsung_div_clock bus2_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) /* DIV_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) /* ENABLE_ACLK_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) /* ENABLE_PCLK_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) ENABLE_PCLK_BUS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #define CMU_BUS_INFO_CLKS(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .div_clks = bus##id##_div_clks, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .gate_clks = bus##id##_gate_clks, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) .nr_clk_ids = BUSx_NR_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static const struct samsung_cmu_info bus0_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) CMU_BUS_INFO_CLKS(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) .clk_regs = bus01_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) static const struct samsung_cmu_info bus1_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) CMU_BUS_INFO_CLKS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .clk_regs = bus01_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) static const struct samsung_cmu_info bus2_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) CMU_BUS_INFO_CLKS(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .mux_clks = bus2_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .clk_regs = bus2_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #define exynos5433_cmu_bus_init(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) samsung_cmu_register_one(np, &bus##id##_cmu_info); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) "samsung,exynos5433-cmu-bus"#id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) exynos5433_cmu_bus##id##_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) exynos5433_cmu_bus_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) exynos5433_cmu_bus_init(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) exynos5433_cmu_bus_init(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) * Register offset definitions for CMU_G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) #define G3D_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) #define G3D_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) #define G3D_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) #define G3D_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) #define MUX_SEL_G3D 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) #define MUX_ENABLE_G3D 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) #define MUX_STAT_G3D 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) #define DIV_G3D 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) #define DIV_G3D_PLL_FREQ_DET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) #define DIV_STAT_G3D 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) #define ENABLE_ACLK_G3D 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) #define ENABLE_PCLK_G3D 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #define ENABLE_SCLK_G3D 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) #define ENABLE_IP_G3D0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) #define ENABLE_IP_G3D1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) #define CLKOUT_CMU_G3D 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) #define CLK_STOPCTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) static const unsigned long g3d_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) G3D_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) G3D_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) G3D_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) G3D_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) MUX_SEL_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) MUX_ENABLE_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) DIV_G3D_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) ENABLE_ACLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) ENABLE_PCLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) ENABLE_SCLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) ENABLE_IP_G3D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) ENABLE_IP_G3D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) CLKOUT_CMU_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) CLKOUT_CMU_G3D_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) CLK_STOPCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) { MUX_SEL_G3D, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) /* MUX_SEL_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static const struct samsung_div_clock g3d_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) /* DIV_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) 0, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) /* ENABLE_ACLK_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) ENABLE_ACLK_G3D, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) ENABLE_ACLK_G3D, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) /* ENABLE_PCLK_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) ENABLE_PCLK_G3D, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) ENABLE_PCLK_G3D, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* ENABLE_SCLK_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) ENABLE_SCLK_G3D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static const struct samsung_cmu_info g3d_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) .pll_clks = g3d_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) .mux_clks = g3d_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .div_clks = g3d_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) .gate_clks = g3d_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) .nr_clk_ids = G3D_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) .clk_regs = g3d_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) .suspend_regs = g3d_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) .clk_name = "aclk_g3d_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) * Register offset definitions for CMU_GSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) #define MUX_SEL_GSCL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) #define MUX_ENABLE_GSCL 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) #define MUX_STAT_GSCL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) #define ENABLE_ACLK_GSCL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) #define ENABLE_PCLK_GSCL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) #define ENABLE_IP_GSCL0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) #define ENABLE_IP_GSCL1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) static const unsigned long gscl_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) MUX_SEL_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) MUX_ENABLE_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) ENABLE_ACLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) ENABLE_PCLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) ENABLE_IP_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) ENABLE_IP_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) { MUX_SEL_GSCL, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) { ENABLE_ACLK_GSCL, 0xfff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) { ENABLE_PCLK_GSCL, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) /* MUX_SEL_GSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) /* ENABLE_ACLK_GSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) ENABLE_ACLK_GSCL, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) ENABLE_ACLK_GSCL, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) ENABLE_ACLK_GSCL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) ENABLE_ACLK_GSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) ENABLE_ACLK_GSCL, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) ENABLE_ACLK_GSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) ENABLE_ACLK_GSCL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) ENABLE_ACLK_GSCL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) /* ENABLE_PCLK_GSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) ENABLE_PCLK_GSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) ENABLE_PCLK_GSCL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) ENABLE_PCLK_GSCL, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) ENABLE_PCLK_GSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) ENABLE_PCLK_GSCL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) ENABLE_PCLK_GSCL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) static const struct samsung_cmu_info gscl_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) .mux_clks = gscl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .gate_clks = gscl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .nr_clk_ids = GSCL_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .clk_regs = gscl_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) .suspend_regs = gscl_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) .clk_name = "aclk_gscl_111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) * Register offset definitions for CMU_APOLLO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) #define APOLLO_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) #define APOLLO_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) #define APOLLO_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) #define APOLLO_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) #define MUX_SEL_APOLLO0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) #define MUX_SEL_APOLLO1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) #define MUX_SEL_APOLLO2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) #define MUX_ENABLE_APOLLO0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) #define MUX_ENABLE_APOLLO1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) #define MUX_ENABLE_APOLLO2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) #define MUX_STAT_APOLLO0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) #define MUX_STAT_APOLLO1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) #define MUX_STAT_APOLLO2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) #define DIV_APOLLO0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) #define DIV_APOLLO1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) #define DIV_APOLLO_PLL_FREQ_DET 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) #define DIV_STAT_APOLLO0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) #define DIV_STAT_APOLLO1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) #define ENABLE_ACLK_APOLLO 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) #define ENABLE_PCLK_APOLLO 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) #define ENABLE_SCLK_APOLLO 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) #define ENABLE_IP_APOLLO0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) #define ENABLE_IP_APOLLO1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) #define CLKOUT_CMU_APOLLO 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) #define ARMCLK_STOPCTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) #define APOLLO_PWR_CTRL 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) #define APOLLO_PWR_CTRL2 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) #define APOLLO_INTR_SPREAD_ENABLE 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) static const unsigned long apollo_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) APOLLO_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) APOLLO_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) APOLLO_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) APOLLO_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) MUX_SEL_APOLLO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) MUX_SEL_APOLLO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) MUX_SEL_APOLLO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) MUX_ENABLE_APOLLO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) MUX_ENABLE_APOLLO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) MUX_ENABLE_APOLLO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) DIV_APOLLO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) DIV_APOLLO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) DIV_APOLLO_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) ENABLE_PCLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) ENABLE_SCLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) ENABLE_IP_APOLLO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) ENABLE_IP_APOLLO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) CLKOUT_CMU_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) CLKOUT_CMU_APOLLO_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) ARMCLK_STOPCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) APOLLO_PWR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) APOLLO_PWR_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) APOLLO_INTR_SPREAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) APOLLO_INTR_SPREAD_USE_STANDBYWFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) APOLLO_INTR_SPREAD_BLOCKING_DURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) PNAME(mout_apollo_p) = { "mout_apollo_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) "mout_bus_pll_apollo_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /* MUX_SEL_APOLLO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) CLK_RECALC_NEW_RATES, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /* MUX_SEL_APOLLO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) /* MUX_SEL_APOLLO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) 0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static const struct samsung_div_clock apollo_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) /* DIV_APOLLO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) /* DIV_APOLLO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) /* ENABLE_ACLK_APOLLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) "div_atclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) "div_atclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) "div_atclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) "div_atclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) "div_aclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) "div_pclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) "div_pclk_apollo", ENABLE_ACLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) /* ENABLE_PCLK_APOLLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) "div_pclk_apollo", ENABLE_PCLK_APOLLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) /* ENABLE_SCLK_APOLLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) ((pclk) << 12) | ((aclk) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) #define E5433_APOLLO_DIV1(hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) (((hpm) << 4) | ((copy) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static void __init exynos5433_cmu_apollo_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) if (!ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) panic("%s: unable to allocate ctx\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) samsung_clk_register_pll(ctx, apollo_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) ARRAY_SIZE(apollo_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) samsung_clk_register_mux(ctx, apollo_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) ARRAY_SIZE(apollo_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) samsung_clk_register_div(ctx, apollo_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) ARRAY_SIZE(apollo_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) samsung_clk_register_gate(ctx, apollo_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) ARRAY_SIZE(apollo_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) CLK_CPU_HAS_E5433_REGS_LAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) samsung_clk_sleep_init(reg_base, apollo_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) ARRAY_SIZE(apollo_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) exynos5433_cmu_apollo_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) * Register offset definitions for CMU_ATLAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) #define ATLAS_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) #define ATLAS_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) #define ATLAS_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) #define ATLAS_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) #define MUX_SEL_ATLAS0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) #define MUX_SEL_ATLAS1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) #define MUX_SEL_ATLAS2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) #define MUX_ENABLE_ATLAS0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) #define MUX_ENABLE_ATLAS1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) #define MUX_ENABLE_ATLAS2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) #define MUX_STAT_ATLAS0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) #define MUX_STAT_ATLAS1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) #define MUX_STAT_ATLAS2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) #define DIV_ATLAS0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) #define DIV_ATLAS1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) #define DIV_ATLAS_PLL_FREQ_DET 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) #define DIV_STAT_ATLAS0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) #define DIV_STAT_ATLAS1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) #define ENABLE_ACLK_ATLAS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) #define ENABLE_PCLK_ATLAS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) #define ENABLE_SCLK_ATLAS 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) #define ENABLE_IP_ATLAS0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) #define ENABLE_IP_ATLAS1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) #define CLKOUT_CMU_ATLAS 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) #define ARMCLK_STOPCTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define ATLAS_PWR_CTRL 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) #define ATLAS_PWR_CTRL2 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) #define ATLAS_INTR_SPREAD_ENABLE 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) static const unsigned long atlas_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) ATLAS_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) ATLAS_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) ATLAS_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) ATLAS_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) MUX_SEL_ATLAS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) MUX_SEL_ATLAS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) MUX_SEL_ATLAS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) MUX_ENABLE_ATLAS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) MUX_ENABLE_ATLAS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) MUX_ENABLE_ATLAS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) DIV_ATLAS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) DIV_ATLAS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) DIV_ATLAS_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) ENABLE_PCLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) ENABLE_SCLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) ENABLE_IP_ATLAS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) ENABLE_IP_ATLAS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) CLKOUT_CMU_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) CLKOUT_CMU_ATLAS_DIV_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) ARMCLK_STOPCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) ATLAS_PWR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) ATLAS_PWR_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) ATLAS_INTR_SPREAD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) ATLAS_INTR_SPREAD_USE_STANDBYWFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) ATLAS_INTR_SPREAD_BLOCKING_DURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) PNAME(mout_atlas_p) = { "mout_atlas_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) "mout_bus_pll_atlas_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /* MUX_SEL_ATLAS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) CLK_RECALC_NEW_RATES, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /* MUX_SEL_ATLAS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /* MUX_SEL_ATLAS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) 0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) static const struct samsung_div_clock atlas_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) /* DIV_ATLAS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) /* DIV_ATLAS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) /* ENABLE_ACLK_ATLAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) "div_atclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) "div_aclk_atlas", ENABLE_ACLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) /* ENABLE_PCLK_ATLAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) /* ENABLE_SCLK_ATLAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) ((pclk) << 12) | ((aclk) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) #define E5433_ATLAS_DIV1(hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) (((hpm) << 4) | ((copy) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) static void __init exynos5433_cmu_atlas_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) if (!ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) panic("%s: unable to allocate ctx\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) samsung_clk_register_pll(ctx, atlas_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) ARRAY_SIZE(atlas_pll_clks), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) samsung_clk_register_mux(ctx, atlas_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) ARRAY_SIZE(atlas_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) samsung_clk_register_div(ctx, atlas_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) ARRAY_SIZE(atlas_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) samsung_clk_register_gate(ctx, atlas_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) ARRAY_SIZE(atlas_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) CLK_CPU_HAS_E5433_REGS_LAYOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) samsung_clk_sleep_init(reg_base, atlas_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) ARRAY_SIZE(atlas_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) exynos5433_cmu_atlas_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) * Register offset definitions for CMU_MSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) #define MUX_SEL_MSCL0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) #define MUX_SEL_MSCL1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) #define MUX_ENABLE_MSCL0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) #define MUX_ENABLE_MSCL1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) #define MUX_STAT_MSCL0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) #define MUX_STAT_MSCL1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) #define DIV_MSCL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) #define DIV_STAT_MSCL 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) #define ENABLE_ACLK_MSCL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) #define ENABLE_PCLK_MSCL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) #define ENABLE_SCLK_MSCL 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) #define ENABLE_IP_MSCL0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) #define ENABLE_IP_MSCL1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) static const unsigned long mscl_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) MUX_SEL_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) MUX_SEL_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) MUX_ENABLE_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) MUX_ENABLE_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) DIV_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) ENABLE_ACLK_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) ENABLE_PCLK_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) ENABLE_SCLK_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) ENABLE_IP_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) ENABLE_IP_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) { MUX_SEL_MSCL0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) { MUX_SEL_MSCL1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) "mout_aclk_mscl_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) /* MUX_SEL_MSCL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) /* MUX_SEL_MSCL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) MUX_SEL_MSCL1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) static const struct samsung_div_clock mscl_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) /* DIV_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) DIV_MSCL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) /* ENABLE_ACLK_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) ENABLE_ACLK_MSCL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) ENABLE_ACLK_MSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) ENABLE_ACLK_MSCL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) ENABLE_ACLK_MSCL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) /* ENABLE_PCLK_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) ENABLE_PCLK_MSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) ENABLE_PCLK_MSCL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) ENABLE_PCLK_MSCL, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) ENABLE_PCLK_MSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) ENABLE_PCLK_MSCL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) ENABLE_PCLK_MSCL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) /* ENABLE_SCLK_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) static const struct samsung_cmu_info mscl_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) .mux_clks = mscl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) .div_clks = mscl_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) .gate_clks = mscl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) .nr_clk_ids = MSCL_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) .clk_regs = mscl_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) .suspend_regs = mscl_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) .clk_name = "aclk_mscl_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) * Register offset definitions for CMU_MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) #define MUX_SEL_MFC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) #define MUX_ENABLE_MFC 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) #define MUX_STAT_MFC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) #define DIV_MFC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) #define DIV_STAT_MFC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) #define ENABLE_ACLK_MFC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) #define ENABLE_PCLK_MFC 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) #define ENABLE_IP_MFC0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) #define ENABLE_IP_MFC1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) static const unsigned long mfc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) MUX_SEL_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) MUX_ENABLE_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) DIV_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) ENABLE_ACLK_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) ENABLE_PCLK_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) ENABLE_IP_MFC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) ENABLE_IP_MFC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) ENABLE_IP_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) { MUX_SEL_MFC, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) /* MUX_SEL_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) static const struct samsung_div_clock mfc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) /* DIV_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) DIV_MFC, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) /* ENABLE_ACLK_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) ENABLE_ACLK_MFC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) ENABLE_ACLK_MFC, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) ENABLE_ACLK_MFC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) /* ENABLE_PCLK_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) ENABLE_PCLK_MFC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) ENABLE_PCLK_MFC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) static const struct samsung_cmu_info mfc_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) .mux_clks = mfc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) .div_clks = mfc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) .gate_clks = mfc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) .nr_clk_ids = MFC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) .clk_regs = mfc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) .suspend_regs = mfc_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) .clk_name = "aclk_mfc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) * Register offset definitions for CMU_HEVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) #define MUX_SEL_HEVC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) #define MUX_ENABLE_HEVC 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) #define MUX_STAT_HEVC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) #define DIV_HEVC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) #define DIV_STAT_HEVC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) #define ENABLE_ACLK_HEVC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) #define ENABLE_PCLK_HEVC 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) #define ENABLE_IP_HEVC0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) #define ENABLE_IP_HEVC1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) static const unsigned long hevc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) MUX_SEL_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) MUX_ENABLE_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) DIV_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) ENABLE_ACLK_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) ENABLE_PCLK_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) ENABLE_IP_HEVC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) ENABLE_IP_HEVC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) { MUX_SEL_HEVC, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) /* MUX_SEL_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) static const struct samsung_div_clock hevc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) /* DIV_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) DIV_HEVC, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) /* ENABLE_ACLK_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) ENABLE_ACLK_HEVC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) ENABLE_ACLK_HEVC, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) ENABLE_ACLK_HEVC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) "mout_aclk_hevc_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) /* ENABLE_PCLK_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) ENABLE_PCLK_HEVC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) ENABLE_PCLK_HEVC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) static const struct samsung_cmu_info hevc_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) .mux_clks = hevc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) .div_clks = hevc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) .gate_clks = hevc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) .nr_clk_ids = HEVC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) .clk_regs = hevc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) .suspend_regs = hevc_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) .clk_name = "aclk_hevc_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) * Register offset definitions for CMU_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) #define MUX_SEL_ISP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) #define MUX_ENABLE_ISP 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) #define MUX_STAT_ISP 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) #define DIV_ISP 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) #define DIV_STAT_ISP 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) #define ENABLE_ACLK_ISP0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) #define ENABLE_ACLK_ISP1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) #define ENABLE_ACLK_ISP2 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) #define ENABLE_PCLK_ISP 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) #define ENABLE_SCLK_ISP 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) #define ENABLE_IP_ISP0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) #define ENABLE_IP_ISP1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) #define ENABLE_IP_ISP2 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) #define ENABLE_IP_ISP3 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) static const unsigned long isp_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) MUX_SEL_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) MUX_ENABLE_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) DIV_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) ENABLE_ACLK_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) ENABLE_ACLK_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) ENABLE_PCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) ENABLE_IP_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) ENABLE_IP_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) ENABLE_IP_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) ENABLE_IP_ISP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) { MUX_SEL_ISP, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) /* MUX_SEL_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) static const struct samsung_div_clock isp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) /* DIV_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) DIV_ISP, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) /* ENABLE_ACLK_ISP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) ENABLE_ACLK_ISP0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) ENABLE_ACLK_ISP0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) ENABLE_ACLK_ISP0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) ENABLE_ACLK_ISP0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) ENABLE_ACLK_ISP0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) ENABLE_ACLK_ISP0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) /* ENABLE_ACLK_ISP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) "div_pclk_isp", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) "div_pclk_isp", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) /* ENABLE_ACLK_ISP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) /* ENABLE_PCLK_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) /* ENABLE_SCLK_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) static const struct samsung_cmu_info isp_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) .mux_clks = isp_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) .div_clks = isp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) .nr_div_clks = ARRAY_SIZE(isp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) .gate_clks = isp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) .nr_clk_ids = ISP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) .clk_regs = isp_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) .suspend_regs = isp_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) .clk_name = "aclk_isp_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) * Register offset definitions for CMU_CAM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) #define MUX_SEL_CAM00 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) #define MUX_SEL_CAM01 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) #define MUX_SEL_CAM02 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) #define MUX_SEL_CAM03 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) #define MUX_SEL_CAM04 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) #define MUX_ENABLE_CAM00 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) #define MUX_ENABLE_CAM01 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) #define MUX_ENABLE_CAM02 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) #define MUX_ENABLE_CAM03 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) #define MUX_ENABLE_CAM04 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) #define MUX_STAT_CAM00 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) #define MUX_STAT_CAM01 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) #define MUX_STAT_CAM02 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) #define MUX_STAT_CAM03 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) #define MUX_STAT_CAM04 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) #define MUX_IGNORE_CAM01 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) #define DIV_CAM00 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) #define DIV_CAM01 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) #define DIV_CAM02 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) #define DIV_CAM03 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) #define DIV_STAT_CAM00 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) #define DIV_STAT_CAM01 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) #define DIV_STAT_CAM02 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) #define DIV_STAT_CAM03 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) #define ENABLE_ACLK_CAM00 0X0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) #define ENABLE_ACLK_CAM01 0X0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) #define ENABLE_ACLK_CAM02 0X0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) #define ENABLE_PCLK_CAM0 0X0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) #define ENABLE_SCLK_CAM0 0X0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) #define ENABLE_IP_CAM00 0X0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) #define ENABLE_IP_CAM01 0X0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) #define ENABLE_IP_CAM02 0X0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) #define ENABLE_IP_CAM03 0X0b0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) static const unsigned long cam0_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) MUX_SEL_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) MUX_SEL_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) MUX_SEL_CAM02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) MUX_SEL_CAM03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) MUX_SEL_CAM04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) MUX_ENABLE_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) MUX_ENABLE_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) MUX_ENABLE_CAM02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) MUX_ENABLE_CAM03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) MUX_ENABLE_CAM04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) MUX_IGNORE_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) DIV_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) DIV_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) DIV_CAM02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) DIV_CAM03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) ENABLE_ACLK_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) ENABLE_ACLK_CAM02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) ENABLE_PCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) ENABLE_SCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) ENABLE_IP_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) ENABLE_IP_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) ENABLE_IP_CAM02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) ENABLE_IP_CAM03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) { MUX_SEL_CAM00, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) { MUX_SEL_CAM01, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) { MUX_SEL_CAM02, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) { MUX_SEL_CAM03, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) { MUX_SEL_CAM04, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) "phyclk_rxbyteclkhs0_s4_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) "phyclk_rxbyteclkhs0_s2a_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) "mout_aclk_cam0_333_user" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) "mout_aclk-cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) "div_pclk_lite_d", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) "div_pclk_pixelasync_lite_c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) "div_pclk_lite_b", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) "mout_aclk_cam0_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) "mout_sclk_pixelasync_lite_c_init_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) "mout_aclk_cam0_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) NULL, 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) /* MUX_SEL_CAM00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) /* MUX_SEL_CAM01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) "mout_phyclk_rxbyteclkhs0_s4_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) mout_phyclk_rxbyteclkhs0_s4_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) MUX_SEL_CAM01, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) "mout_phyclk_rxbyteclkhs0_s2a_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) mout_phyclk_rxbyteclkhs0_s2a_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) MUX_SEL_CAM01, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) /* MUX_SEL_CAM02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) MUX_SEL_CAM02, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) MUX_SEL_CAM02, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) MUX_SEL_CAM02, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) MUX_SEL_CAM02, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) MUX_SEL_CAM02, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) MUX_SEL_CAM02, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) MUX_SEL_CAM02, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) /* MUX_SEL_CAM03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) MUX_SEL_CAM03, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) MUX_SEL_CAM03, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) MUX_SEL_CAM03, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) MUX_SEL_CAM03, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) MUX_SEL_CAM03, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) MUX_SEL_CAM03, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) MUX_SEL_CAM03, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) MUX_SEL_CAM03, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) /* MUX_SEL_CAM04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) "mout_sclk_pixelasync_lite_c_init_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) mout_sclk_pixelasync_lite_c_init_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) MUX_SEL_CAM04, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) "mout_sclk_pixelasync_lite_c_init_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) mout_sclk_pixelasync_lite_c_init_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) MUX_SEL_CAM04, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) static const struct samsung_div_clock cam0_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) /* DIV_CAM00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) DIV_CAM00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) DIV_CAM00, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) /* DIV_CAM01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) DIV_CAM01, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) DIV_CAM01, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) DIV_CAM01, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) DIV_CAM01, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) DIV_CAM01, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) DIV_CAM01, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) /* DIV_CAM02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) DIV_CAM02, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) DIV_CAM02, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) DIV_CAM02, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) DIV_CAM02, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) DIV_CAM02, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) DIV_CAM02, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) /* DIV_CAM03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) "div_sclk_pixelasync_lite_c_init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) /* ENABLE_ACLK_CAM00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) ENABLE_ACLK_CAM00, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) ENABLE_ACLK_CAM00, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) ENABLE_ACLK_CAM00, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) /* ENABLE_ACLK_CAM01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) "div_pclk_lite_d", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) "div_pclk_lite_b", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) "div_pclk_lite_a", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) "div_aclk_3aa1", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) "div_aclk_3aa0", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) "div_aclk_lite_d", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) "div_aclk_lite_b", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) "div_aclk_lite_a", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) /* ENABLE_ACLK_CAM02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) /* ENABLE_PCLK_CAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) /* ENABLE_SCLK_CAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) "mout_phyclk_rxbyteclkhs0_s4_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) ENABLE_SCLK_CAM0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) "mout_phyclk_rxbyteclkhs0_s2a_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) ENABLE_SCLK_CAM0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) "div_sclk_pixelasync_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) ENABLE_SCLK_CAM0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) "div_sclk_pixelasync_lite_c_init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) ENABLE_SCLK_CAM0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) "div_sclk_pixelasync_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) ENABLE_SCLK_CAM0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) static const struct samsung_cmu_info cam0_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) .mux_clks = cam0_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) .div_clks = cam0_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) .gate_clks = cam0_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) .fixed_clks = cam0_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) .nr_clk_ids = CAM0_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) .clk_regs = cam0_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) .suspend_regs = cam0_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) .clk_name = "aclk_cam0_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) * Register offset definitions for CMU_CAM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) #define MUX_SEL_CAM10 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) #define MUX_SEL_CAM11 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) #define MUX_SEL_CAM12 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) #define MUX_ENABLE_CAM10 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) #define MUX_ENABLE_CAM11 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) #define MUX_ENABLE_CAM12 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) #define MUX_STAT_CAM10 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) #define MUX_STAT_CAM11 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) #define MUX_STAT_CAM12 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) #define MUX_IGNORE_CAM11 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) #define DIV_CAM10 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) #define DIV_CAM11 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) #define DIV_STAT_CAM10 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) #define DIV_STAT_CAM11 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) #define ENABLE_ACLK_CAM10 0X0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) #define ENABLE_ACLK_CAM11 0X0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) #define ENABLE_ACLK_CAM12 0X0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) #define ENABLE_PCLK_CAM1 0X0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) #define ENABLE_SCLK_CAM1 0X0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) #define ENABLE_IP_CAM10 0X0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) #define ENABLE_IP_CAM11 0X0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) #define ENABLE_IP_CAM12 0X0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) static const unsigned long cam1_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) MUX_SEL_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) MUX_SEL_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) MUX_SEL_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) MUX_ENABLE_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) MUX_ENABLE_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) MUX_ENABLE_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) MUX_IGNORE_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) DIV_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) DIV_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) ENABLE_ACLK_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) ENABLE_PCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) ENABLE_SCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) ENABLE_IP_CAM10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) ENABLE_IP_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) ENABLE_IP_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) { MUX_SEL_CAM10, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) { MUX_SEL_CAM11, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) { MUX_SEL_CAM12, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) "phyclk_rxbyteclkhs0_s2b_phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) "mout_aclk_cam1_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) "mout_aclk_cam1_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) "mout_aclk_cam1_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) "mout_aclk_cam1_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) "mout_aclk_cam1_333_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) "mout_aclk_cam1_400_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) 0, 100000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /* MUX_SEL_CAM10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /* MUX_SEL_CAM11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) "mout_phyclk_rxbyteclkhs0_s2b_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) mout_phyclk_rxbyteclkhs0_s2b_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) MUX_SEL_CAM11, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) /* MUX_SEL_CAM12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) MUX_SEL_CAM12, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) MUX_SEL_CAM12, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) MUX_SEL_CAM12, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) MUX_SEL_CAM12, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) MUX_SEL_CAM12, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) MUX_SEL_CAM12, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) static const struct samsung_div_clock cam1_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) /* DIV_CAM10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) "div_pclk_cam1_83", DIV_CAM10, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) DIV_CAM10, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) /* DIV_CAM11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) DIV_CAM11, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) DIV_CAM11, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) DIV_CAM11, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) /* ENABLE_ACLK_CAM10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) ENABLE_ACLK_CAM10, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) ENABLE_ACLK_CAM10, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) ENABLE_ACLK_CAM10, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) ENABLE_ACLK_CAM10, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) /* ENABLE_ACLK_CAM11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) "div_pclk_lite_c", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) "div_aclk_lite_c", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) /* ENABLE_ACLK_CAM12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) /* ENABLE_PCLK_CAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) /* ENABLE_SCLK_CAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) "mout_phyclk_rxbyteclkhs0_s2b_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) ENABLE_SCLK_CAM1, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) ENABLE_SCLK_CAM1, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) ENABLE_SCLK_CAM1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) ENABLE_SCLK_CAM1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) ENABLE_SCLK_CAM1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) ENABLE_SCLK_CAM1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) ENABLE_SCLK_CAM1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) ENABLE_SCLK_CAM1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) ENABLE_SCLK_CAM1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) ENABLE_SCLK_CAM1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) ENABLE_SCLK_CAM1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) static const struct samsung_cmu_info cam1_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) .mux_clks = cam1_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) .div_clks = cam1_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) .gate_clks = cam1_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) .fixed_clks = cam1_fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) .nr_clk_ids = CAM1_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) .clk_regs = cam1_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) .suspend_regs = cam1_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) .clk_name = "aclk_cam1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) * Register offset definitions for CMU_IMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) #define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) static const unsigned long imem_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) ENABLE_ACLK_IMEM_SLIMSSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) ENABLE_PCLK_IMEM_SLIMSSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) /* ENABLE_ACLK_IMEM_SLIMSSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) /* ENABLE_PCLK_IMEM_SLIMSSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) static const struct samsung_cmu_info imem_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) .gate_clks = imem_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) .nr_clk_ids = IMEM_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) .clk_regs = imem_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) .clk_name = "aclk_imem_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) struct exynos5433_cmu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) struct samsung_clk_reg_dump *clk_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) unsigned int nr_clk_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) const struct samsung_clk_reg_dump *clk_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) unsigned int nr_clk_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) struct clk **pclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) int nr_pclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) struct samsung_clk_provider ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) samsung_clk_save(data->ctx.reg_base, data->clk_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) data->nr_clk_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) for (i = 0; i < data->nr_pclks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) clk_prepare_enable(data->pclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) /* for suspend some registers have to be set to certain values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) data->nr_clk_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) for (i = 0; i < data->nr_pclks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) clk_disable_unprepare(data->pclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) clk_disable_unprepare(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) for (i = 0; i < data->nr_pclks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) clk_prepare_enable(data->pclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) samsung_clk_restore(data->ctx.reg_base, data->clk_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) data->nr_clk_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) for (i = 0; i < data->nr_pclks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) clk_disable_unprepare(data->pclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) static int __init exynos5433_cmu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) const struct samsung_cmu_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) struct exynos5433_cmu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) info = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) data = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) ctx = &data->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) for (i = 0; i < info->nr_clk_ids; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) ctx->clk_data.num = info->nr_clk_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) ctx->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) spin_lock_init(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) info->nr_clk_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) if (!data->clk_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) data->nr_clk_save = info->nr_clk_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) data->clk_suspend = info->suspend_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) data->nr_clk_suspend = info->nr_suspend_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) data->nr_pclks = of_clk_get_parent_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) if (data->nr_pclks > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) data->nr_pclks, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) if (!data->pclks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) kfree(data->clk_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) for (i = 0; i < data->nr_pclks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) struct clk *clk = of_clk_get(dev->of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) kfree(data->clk_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) clk_put(data->pclks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) data->pclks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) if (info->clk_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) data->clk = clk_get(dev, info->clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) * Enable runtime PM here to allow the clock core using runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) * for the registered clocks. Additionally, we increase the runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) * PM usage count before registering the clocks, to prevent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) * clock core from runtime suspending the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) if (info->pll_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) if (info->mux_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) samsung_clk_register_mux(ctx, info->mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) info->nr_mux_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) if (info->div_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) samsung_clk_register_div(ctx, info->div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) info->nr_div_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) if (info->gate_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) samsung_clk_register_gate(ctx, info->gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) info->nr_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) if (info->fixed_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) info->nr_fixed_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) if (info->fixed_factor_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) info->nr_fixed_factor_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) samsung_clk_of_add_provider(dev->of_node, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) static const struct of_device_id exynos5433_cmu_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) .compatible = "samsung,exynos5433-cmu-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) .data = &aud_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) .compatible = "samsung,exynos5433-cmu-cam0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) .data = &cam0_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) .compatible = "samsung,exynos5433-cmu-cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) .data = &cam1_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) .compatible = "samsung,exynos5433-cmu-disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) .data = &disp_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) .compatible = "samsung,exynos5433-cmu-g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) .data = &g2d_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) .compatible = "samsung,exynos5433-cmu-g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) .data = &g3d_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) .compatible = "samsung,exynos5433-cmu-fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) .data = &fsys_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) .compatible = "samsung,exynos5433-cmu-gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) .data = &gscl_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) .compatible = "samsung,exynos5433-cmu-mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) .data = &mfc_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) .compatible = "samsung,exynos5433-cmu-hevc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) .data = &hevc_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) .compatible = "samsung,exynos5433-cmu-isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) .data = &isp_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) .compatible = "samsung,exynos5433-cmu-mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) .data = &mscl_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) .compatible = "samsung,exynos5433-cmu-imem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) .data = &imem_cmu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) static struct platform_driver exynos5433_cmu_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) .name = "exynos5433-cmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) .of_match_table = exynos5433_cmu_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) .pm = &exynos5433_cmu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) .probe = exynos5433_cmu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) static int __init exynos5433_cmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) return platform_driver_register(&exynos5433_cmu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) core_initcall(exynos5433_cmu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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