^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chander Kashyap <k.chander@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Common Clock Framework support for Exynos5420 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/exynos5420.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-exynos5-subcmu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APLL_LOCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APLL_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRC_CPU 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DIV_CPU0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DIV_CPU1 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GATE_BUS_CPU 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GATE_SCLK_CPU 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKOUT_CMU_CPU 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SRC_MASK_CPERI 0x4300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GATE_IP_G2D 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPLL_LOCK 0x10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPLL_LOCK 0x10030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EPLL_LOCK 0x10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RPLL_LOCK 0x10050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPLL_LOCK 0x10060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPLL_LOCK 0x10070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VPLL_LOCK 0x10080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPLL_LOCK 0x10090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPLL_CON0 0x10120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPLL_CON0 0x10128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EPLL_CON0 0x10130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EPLL_CON1 0x10134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EPLL_CON2 0x10138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RPLL_CON0 0x10140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RPLL_CON1 0x10144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RPLL_CON2 0x10148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPLL_CON0 0x10150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPLL_CON0 0x10160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VPLL_CON0 0x10170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPLL_CON0 0x10180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRC_TOP0 0x10200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRC_TOP1 0x10204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_TOP2 0x10208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRC_TOP3 0x1020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_TOP4 0x10210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRC_TOP5 0x10214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRC_TOP6 0x10218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRC_TOP7 0x1021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SRC_TOP8 0x10220 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SRC_TOP9 0x10224 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SRC_DISP10 0x1022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRC_MAU 0x10240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SRC_FSYS 0x10244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SRC_PERIC0 0x10250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SRC_PERIC1 0x10254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SRC_ISP 0x10270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SRC_CAM 0x10274 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SRC_TOP10 0x10280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SRC_TOP11 0x10284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SRC_TOP12 0x10288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SRC_TOP13 0x1028c /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SRC_MASK_TOP0 0x10300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SRC_MASK_TOP1 0x10304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SRC_MASK_TOP2 0x10308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SRC_MASK_TOP7 0x1031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SRC_MASK_DISP10 0x1032c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SRC_MASK_MAU 0x10334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SRC_MASK_FSYS 0x10340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SRC_MASK_PERIC0 0x10350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SRC_MASK_PERIC1 0x10354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SRC_MASK_ISP 0x10370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DIV_TOP0 0x10500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DIV_TOP1 0x10504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DIV_TOP2 0x10508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DIV_TOP8 0x10520 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DIV_TOP9 0x10524 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DIV_DISP10 0x1052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DIV_MAU 0x10544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DIV_FSYS0 0x10548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DIV_FSYS1 0x1054c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DIV_FSYS2 0x10550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DIV_PERIC0 0x10558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DIV_PERIC1 0x1055c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DIV_PERIC2 0x10560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DIV_PERIC3 0x10564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DIV_PERIC4 0x10568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DIV_CAM 0x10574 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCLK_DIV_ISP0 0x10580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCLK_DIV_ISP1 0x10584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DIV2_RATIO0 0x10590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DIV4_RATIO 0x105a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GATE_BUS_TOP 0x10700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GATE_BUS_DISP1 0x10728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GATE_BUS_GEN 0x1073c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GATE_BUS_FSYS0 0x10740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GATE_BUS_FSYS2 0x10748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GATE_BUS_PERIC 0x10750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GATE_BUS_PERIC1 0x10754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GATE_BUS_PERIS0 0x10760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GATE_BUS_PERIS1 0x10764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GATE_BUS_NOC 0x10770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GATE_TOP_SCLK_ISP 0x10870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GATE_IP_GSCL0 0x10910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GATE_IP_GSCL1 0x10920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GATE_IP_CAM 0x10924 /* 5800 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GATE_IP_MFC 0x1092c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GATE_IP_DISP1 0x10928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GATE_IP_G3D 0x10930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GATE_IP_GEN 0x10934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GATE_IP_FSYS 0x10944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GATE_IP_PERIC 0x10950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GATE_IP_PERIS 0x10960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GATE_IP_MSCL 0x10970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GATE_TOP_SCLK_GSCL 0x10820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GATE_TOP_SCLK_DISP1 0x10828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GATE_TOP_SCLK_MAU 0x1083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GATE_TOP_SCLK_FSYS 0x10840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GATE_TOP_SCLK_PERIC 0x10850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TOP_SPARE2 0x10b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BPLL_LOCK 0x20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BPLL_CON0 0x20110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SRC_CDREX 0x20200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DIV_CDREX0 0x20500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DIV_CDREX1 0x20504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GATE_BUS_CDREX0 0x20700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GATE_BUS_CDREX1 0x20704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define KPLL_LOCK 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define KPLL_CON0 0x28100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SRC_KFC 0x28200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DIV_KFC0 0x28500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Exynos5x SoC type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum exynos5x_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EXYNOS5420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) EXYNOS5800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* list of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum exynos5x_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bpll, kpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) nr_plls /* number of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static enum exynos5x_soc exynos5x_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned long exynos5x_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SRC_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DIV_CPU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DIV_CPU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GATE_BUS_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GATE_SCLK_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CLKOUT_CMU_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) APLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) KPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) EPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) VPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SRC_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SRC_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SRC_TOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SRC_TOP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SRC_TOP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SRC_TOP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SRC_TOP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SRC_DISP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SRC_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SRC_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SRC_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SRC_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SRC_TOP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SRC_TOP11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SRC_TOP12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SRC_MASK_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SRC_MASK_TOP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SRC_MASK_DISP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SRC_MASK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SRC_MASK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SRC_MASK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SRC_MASK_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SRC_MASK_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SRC_MASK_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SRC_MASK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SRC_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DIV_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DIV_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DIV_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DIV_DISP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DIV_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DIV_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DIV_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DIV_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DIV_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DIV_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DIV_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DIV_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DIV_PERIC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SCLK_DIV_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SCLK_DIV_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DIV2_RATIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DIV4_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GATE_BUS_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GATE_BUS_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GATE_BUS_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GATE_BUS_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GATE_BUS_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GATE_BUS_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GATE_BUS_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GATE_BUS_PERIS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GATE_BUS_PERIS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GATE_BUS_NOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GATE_TOP_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GATE_IP_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GATE_IP_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GATE_IP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GATE_IP_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GATE_IP_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GATE_IP_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GATE_IP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GATE_IP_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GATE_IP_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GATE_IP_MSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GATE_TOP_SCLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GATE_TOP_SCLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GATE_TOP_SCLK_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GATE_TOP_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GATE_TOP_SCLK_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TOP_SPARE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SRC_CDREX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DIV_CDREX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DIV_CDREX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SRC_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DIV_KFC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GATE_BUS_CDREX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GATE_BUS_CDREX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned long exynos5800_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SRC_TOP8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SRC_TOP9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SRC_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DIV_TOP8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DIV_TOP9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DIV_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) GATE_IP_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { .offset = SRC_MASK_MAU, .value = 0x10000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .offset = SRC_MASK_ISP, .value = 0x11111000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* list of all parent clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "mout_sclk_mpll", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "mout_sclk_mpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "mout_sclk_epll", "mout_sclk_rpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "mout_sclk_mpll", "mout_sclk_spll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* List of parents specific to exynos5800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "mout_sclk_mpll", "ff_dout_spll2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "mout_sclk_mpll", "ff_dout_spll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "mout_epll2", "mout_sclk_ipll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "mout_sclk_mpll", "ff_dout_spll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "mout_epll2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "mout_sclk_mpll", "mout_sclk_spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "mout_sclk_mpll", "ff_dout_spll2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "mout_sclk_mpll", "mout_sclk_spll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "mout_epll2", "mout_sclk_ipll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "mout_sclk_mpll", "ff_dout_spll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "mout_sclk_spll", "mout_sclk_epll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "mout_sclk_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "ff_dout_spll2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "mout_sclk_mpll", "ff_dout_spll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "mout_sclk_spll", "mout_sclk_epll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* fixed rate clocks generated outside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct samsung_fixed_rate_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) exynos5x_fixed_rate_ext_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* fixed rate clocks generated inside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) FRATE(0, "sclk_pwi", NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct samsung_fixed_factor_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) exynos5x_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct samsung_fixed_factor_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) exynos5800_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SRC_TOP9, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SRC_TOP9, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SRC_TOP9, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SRC_TOP9, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SRC_TOP13, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SRC_TOP13, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SRC_TOP13, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "mout_aclk400_wcore", DIV_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) DIV_TOP8, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DIV_TOP8, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DIV_TOP8, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DIV_TOP8, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) TOP_SPARE2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX(0, "mout_aclk333_432_isp", mout_group4_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SRC_TOP1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mout_group5_5800_p, SRC_TOP7, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Maudio Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SRC_TOP7, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SRC_TOP7, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SRC_TOP7, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SRC_TOP3, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SRC_TOP3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SRC_TOP3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SRC_TOP3, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SRC_TOP3, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SRC_TOP3, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SRC_TOP3, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SRC_TOP4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SRC_TOP4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SRC_TOP4, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SRC_TOP4, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SRC_TOP4, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SRC_TOP4, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SRC_TOP5, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SRC_TOP5, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SRC_TOP5, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SRC_TOP5, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SRC_TOP10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SRC_TOP10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SRC_TOP10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) SRC_TOP10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) SRC_TOP10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SRC_TOP10, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SRC_TOP10, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SRC_TOP10, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SRC_TOP11, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SRC_TOP11, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SRC_TOP11, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) SRC_TOP11, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SRC_TOP12, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SRC_TOP12, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SRC_TOP12, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* DISP1 Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* CDREX block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* MAU Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* FSYS Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* PERIC Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* ISP Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DIV_TOP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DIV_TOP0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DIV_TOP0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DIV_TOP0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DIV_TOP0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DIV_TOP0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DIV_TOP0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DIV_TOP1, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DIV_TOP1, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DIV_TOP1, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DIV_TOP1, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) DIV_TOP2, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) DIV_TOP2, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 16, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DIV_TOP2, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "mout_aclk300_disp1", DIV_TOP2, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) DIV_TOP2, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* DISP1 Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "mout_aclk400_disp1", DIV_TOP2, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* CDREX Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * The three clocks below are controlled using the same register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * bits. They are put into one because there is a need of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * synchronization between the BUS and DREXs (two external memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * interfaces).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * They are put here to show this HW assumption and for clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * information summary completeness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) DIV_CDREX0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DIV_CDREX0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DIV_CDREX0, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) DIV_CDREX1, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Audio Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* USB3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* UART and PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Audio - I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* SPI Pre-Ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* GSCL Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* PSGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* ISP Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) GATE(0, "aclk166", "mout_user_aclk166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE_BUS_TOP, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE_BUS_TOP, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* sclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Display */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GATE_TOP_SCLK_DISP1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* FSYS Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* PERIC Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GATE_IP_PERIC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GATE_IP_PERIC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) GATE_IP_PERIC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GATE_IP_PERIC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GATE_IP_PERIC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GATE_IP_PERIC, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GATE_IP_PERIC, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GATE_IP_PERIC, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) GATE_IP_PERIC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) GATE_IP_PERIC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GATE_IP_PERIC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GATE_IP_PERIC, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) GATE_IP_PERIC, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) GATE_IP_PERIC, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GATE_IP_PERIC, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GATE_IP_PERIC, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GATE_IP_PERIC, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GATE_IP_PERIC, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) GATE_IP_PERIC, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GATE_IP_PERIC, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GATE_IP_PERIC, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) GATE_IP_PERIC, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) GATE_IP_PERIC, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GATE_IP_PERIC, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE_IP_PERIC, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GATE_IP_PERIC, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) GATE_BUS_PERIC, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* PERIS Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* GEN Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GATE_IP_GEN, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) GATE_IP_GEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) GATE_BUS_GEN, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* GSCL Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) GATE_TOP_SCLK_GSCL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) GATE_TOP_SCLK_GSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) GATE_IP_GSCL0, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) GATE_IP_GSCL0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) GATE_IP_GSCL0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) GATE_IP_GSCL1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) GATE_IP_GSCL1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE_IP_GSCL1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) CLK_IS_CRITICAL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) GATE_IP_GSCL1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) GATE_IP_GSCL1, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* CDREX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GATE_BUS_CDREX0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) GATE_BUS_CDREX0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) GATE_IP_DISP1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) GATE_IP_DISP1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) GATE_IP_DISP1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DIV2_RATIO0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) GATE_IP_GSCL1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) GATE_IP_GSCL1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* MSCL Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) GATE_IP_MSCL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) GATE_IP_MSCL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) GATE_IP_MSCL, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .div_clks = exynos5x_disp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .gate_clks = exynos5x_disp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .suspend_regs = exynos5x_disp_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .pd_name = "DISP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .div_clks = exynos5x_gsc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .gate_clks = exynos5x_gsc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .suspend_regs = exynos5x_gsc_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .pd_name = "GSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .gate_clks = exynos5x_g3d_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .suspend_regs = exynos5x_g3d_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .pd_name = "G3D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .div_clks = exynos5x_mfc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .gate_clks = exynos5x_mfc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .suspend_regs = exynos5x_mfc_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .pd_name = "MFC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .div_clks = exynos5x_mscl_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .gate_clks = exynos5x_mscl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .suspend_regs = exynos5x_mscl_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .pd_name = "MSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .gate_clks = exynos5800_mau_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .suspend_regs = exynos5800_mau_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .pd_name = "MAU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) &exynos5x_disp_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) &exynos5x_gsc_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) &exynos5x_g3d_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) &exynos5x_mfc_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) &exynos5x_mscl_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) &exynos5x_disp_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) &exynos5x_gsc_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) &exynos5x_g3d_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) &exynos5x_mfc_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) &exynos5x_mscl_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) &exynos5800_mau_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) CPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) DPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) RPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) IPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) SPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) VPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) MPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) BPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) KPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ((cpud) << 4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define E5420_KFC_DIV(kpll, pclk, aclk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { 1300000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) { 1200000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) { 1100000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) { 1000000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) { 900000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) { 800000, E5420_KFC_DIV(3, 5, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) { 700000, E5420_KFC_DIV(3, 4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) { 600000, E5420_KFC_DIV(3, 4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) { 500000, E5420_KFC_DIV(3, 4, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) { 400000, E5420_KFC_DIV(3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) { 300000, E5420_KFC_DIV(3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) { 200000, E5420_KFC_DIV(3, 3, 2), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const struct of_device_id ext_clk_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* register exynos5420 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static void __init exynos5x_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) enum exynos5x_soc soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) panic("%s: unable to determine soc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) exynos5x_soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ext_clk_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (_get_rate("fin_pll") == 24 * MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (soc == EXYNOS5420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ARRAY_SIZE(exynos5x_fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ARRAY_SIZE(exynos5x_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) samsung_clk_register_mux(ctx, exynos5x_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ARRAY_SIZE(exynos5x_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) samsung_clk_register_div(ctx, exynos5x_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ARRAY_SIZE(exynos5x_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) samsung_clk_register_gate(ctx, exynos5x_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ARRAY_SIZE(exynos5x_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (soc == EXYNOS5420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) samsung_clk_register_mux(ctx, exynos5420_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ARRAY_SIZE(exynos5420_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) samsung_clk_register_div(ctx, exynos5420_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ARRAY_SIZE(exynos5420_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) samsung_clk_register_gate(ctx, exynos5420_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ARRAY_SIZE(exynos5420_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) samsung_clk_register_fixed_factor(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) ctx, exynos5800_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ARRAY_SIZE(exynos5800_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) samsung_clk_register_mux(ctx, exynos5800_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ARRAY_SIZE(exynos5800_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) samsung_clk_register_div(ctx, exynos5800_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ARRAY_SIZE(exynos5800_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) samsung_clk_register_gate(ctx, exynos5800_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ARRAY_SIZE(exynos5800_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (soc == EXYNOS5420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) samsung_clk_extended_sleep_init(reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (soc == EXYNOS5800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ARRAY_SIZE(exynos5800_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) exynos5800_subcmus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) exynos5x_subcmus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * Keep top part of G3D clock path enabled permanently to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * that the internal busses get their clock regardless of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * main G3D clock enablement status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * Keep top BPLL mux enabled permanently to ensure that DRAM operates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static void __init exynos5420_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) exynos5x_clk_init(np, EXYNOS5420);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) exynos5420_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static void __init exynos5800_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) exynos5x_clk_init(np, EXYNOS5800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) exynos5800_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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