^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Tarek Dakhran <t.dakhran@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for Exynos5410 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/clock/exynos5410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define APLL_LOCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APLL_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPLL_LOCK 0x10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPLL_CON0 0x10120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EPLL_LOCK 0x10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EPLL_CON0 0x10130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPLL_LOCK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPLL_CON0 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BPLL_LOCK 0x20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BPLL_CON0 0x20110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define KPLL_LOCK 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define KPLL_CON0 0x28100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SRC_CPU 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DIV_CPU0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SRC_CPERI1 0x4204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GATE_IP_G2D 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DIV_TOP0 0x10510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DIV_TOP1 0x10514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DIV_FSYS0 0x10548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DIV_FSYS1 0x1054c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DIV_FSYS2 0x10550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DIV_PERIC0 0x10558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DIV_PERIC3 0x10564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_TOP0 0x10210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_TOP1 0x10214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_TOP2 0x10218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_FSYS 0x10244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SRC_PERIC0 0x10250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRC_MASK_FSYS 0x10340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRC_MASK_PERIC0 0x10350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GATE_BUS_FSYS0 0x10740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GATE_TOP_SCLK_FSYS 0x10840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GATE_TOP_SCLK_PERIC 0x10850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GATE_IP_FSYS 0x10944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GATE_IP_PERIC 0x10950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GATE_IP_PERIS 0x10960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_CDREX 0x20200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRC_KFC 0x28200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DIV_KFC0 0x28500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* list of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum exynos5410_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) apll, cpll, epll, mpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bpll, kpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) nr_plls /* number of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* list of all parent clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PNAME(apll_p) = { "fin_pll", "fout_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PNAME(epll_p) = { "fin_pll", "fout_epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "none", "none", "sclk_mpll_bpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "none", "none", "sclk_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DIV_F(0, "div_mmc_pre0", "div_mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DIV_F(0, "div_mmc_pre1", "div_mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DIV_F(0, "div_mmc_pre2", "div_mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) KPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct samsung_cmu_info cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pll_clks = exynos5410_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .nr_pll_clks = ARRAY_SIZE(exynos5410_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .mux_clks = exynos5410_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .nr_mux_clks = ARRAY_SIZE(exynos5410_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .div_clks = exynos5410_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .gate_clks = exynos5410_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .nr_clk_ids = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* register exynos5410 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void __init exynos5410_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct clk *xxti = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) samsung_cmu_register_one(np, &cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_debug("Exynos5410: clock setup completed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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