^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Rahul Sharma <rahul.sharma@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for Exynos5260 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __CLK_EXYNOS5260_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __CLK_EXYNOS5260_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *Registers for CMU_AUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MUX_SEL_AUD 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MUX_ENABLE_AUD 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MUX_STAT_AUD 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MUX_IGNORE_AUD 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DIV_AUD0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DIV_AUD1 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DIV_STAT_AUD0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DIV_STAT_AUD1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EN_ACLK_AUD 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EN_PCLK_AUD 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EN_SCLK_AUD 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EN_IP_AUD 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *Registers for CMU_DISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MUX_SEL_DISP0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MUX_SEL_DISP1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MUX_SEL_DISP2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MUX_SEL_DISP3 0x020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MUX_SEL_DISP4 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MUX_ENABLE_DISP0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MUX_ENABLE_DISP1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MUX_ENABLE_DISP2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MUX_ENABLE_DISP3 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MUX_ENABLE_DISP4 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_STAT_DISP0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUX_STAT_DISP1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MUX_STAT_DISP2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MUX_STAT_DISP3 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MUX_STAT_DISP4 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MUX_IGNORE_DISP0 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MUX_IGNORE_DISP1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MUX_IGNORE_DISP2 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MUX_IGNORE_DISP3 0x050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MUX_IGNORE_DISP4 0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DIV_DISP 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DIV_STAT_DISP 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EN_ACLK_DISP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EN_PCLK_DISP 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EN_SCLK_DISP0 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EN_SCLK_DISP1 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EN_IP_DISP 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EN_IP_DISP_BUS 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *Registers for CMU_EGL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EGL_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EGL_DPLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EGL_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EGL_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EGL_PLL_FREQ_DET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EGL_DPLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EGL_DPLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EGL_DPLL_FREQ_DET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MUX_SEL_EGL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MUX_ENABLE_EGL 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MUX_STAT_EGL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DIV_EGL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DIV_EGL_PLL_FDET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DIV_STAT_EGL 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DIV_STAT_EGL_PLL_FDET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EN_ACLK_EGL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EN_PCLK_EGL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EN_SCLK_EGL 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EN_IP_EGL 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLKOUT_CMU_EGL 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLKOUT_CMU_EGL_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ARMCLK_STOPCTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EAGLE_EMA_CTRL 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EAGLE_EMA_STATUS 0x100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PWR_CTRL 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PWR_CTRL2 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLKSTOP_CTRL 0x1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define INTR_SPREAD_EN 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define INTR_SPREAD_USE_STANDBYWFI 0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INTR_SPREAD_BLOCKING_DURATION 0x1088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMU_EGL_SPARE0 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMU_EGL_SPARE1 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMU_EGL_SPARE2 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMU_EGL_SPARE3 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMU_EGL_SPARE4 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *Registers for CMU_FSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MUX_SEL_FSYS0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MUX_SEL_FSYS1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MUX_ENABLE_FSYS0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MUX_ENABLE_FSYS1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MUX_STAT_FSYS0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MUX_STAT_FSYS1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MUX_IGNORE_FSYS0 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MUX_IGNORE_FSYS1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EN_ACLK_FSYS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EN_ACLK_FSYS_SECURE_RTIC 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EN_PCLK_FSYS 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EN_SCLK_FSYS 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EN_IP_FSYS 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EN_IP_FSYS_SECURE_RTIC 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *Registers for CMU_G2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MUX_SEL_G2D 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MUX_ENABLE_G2D 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MUX_STAT_G2D 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DIV_G2D 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DIV_STAT_G2D 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EN_ACLK_G2D 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EN_ACLK_G2D_SECURE_SSS 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EN_PCLK_G2D 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EN_IP_G2D 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EN_IP_G2D_SECURE_SSS 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *Registers for CMU_G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define G3D_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define G3D_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define G3D_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define G3D_PLL_FDET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MUX_SEL_G3D 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MUX_EN_G3D 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MUX_STAT_G3D 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MUX_IGNORE_G3D 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DIV_G3D 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DIV_G3D_PLL_FDET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DIV_STAT_G3D 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DIV_STAT_G3D_PLL_FDET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EN_ACLK_G3D 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EN_PCLK_G3D 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EN_SCLK_G3D 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EN_IP_G3D 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLKOUT_CMU_G3D 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define G3DCLK_STOPCTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define G3D_EMA_CTRL 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define G3D_EMA_STATUS 0x100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *Registers for CMU_GSCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MUX_SEL_GSCL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MUX_EN_GSCL 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MUX_STAT_GSCL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MUX_IGNORE_GSCL 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DIV_GSCL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DIV_STAT_GSCL 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EN_ACLK_GSCL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EN_ACLK_GSCL_FIMC 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EN_PCLK_GSCL 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EN_PCLK_GSCL_FIMC 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EN_SCLK_GSCL 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EN_SCLK_GSCL_FIMC 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EN_IP_GSCL 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EN_IP_GSCL_FIMC 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *Registers for CMU_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MUX_SEL_ISP0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MUX_SEL_ISP1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MUX_ENABLE_ISP0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MUX_ENABLE_ISP1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MUX_STAT_ISP0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MUX_STAT_ISP1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MUX_IGNORE_ISP0 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MUX_IGNORE_ISP1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DIV_ISP 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DIV_STAT_ISP 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EN_ACLK_ISP0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EN_ACLK_ISP1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EN_PCLK_ISP0 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EN_PCLK_ISP1 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define EN_SCLK_ISP 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EN_IP_ISP0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EN_IP_ISP1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *Registers for CMU_KFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define KFC_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define KFC_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define KFC_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define KFC_PLL_FDET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MUX_SEL_KFC0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MUX_SEL_KFC2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MUX_ENABLE_KFC0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MUX_ENABLE_KFC2 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MUX_STAT_KFC0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MUX_STAT_KFC2 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DIV_KFC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DIV_KFC_PLL_FDET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DIV_STAT_KFC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DIV_STAT_KFC_PLL_FDET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EN_ACLK_KFC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EN_PCLK_KFC 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EN_SCLK_KFC 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EN_IP_KFC 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLKOUT_CMU_KFC 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLKOUT_CMU_KFC_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ARMCLK_STOPCTRL_KFC 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ARM_EMA_CTRL 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ARM_EMA_STATUS 0x100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PWR_CTRL_KFC 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PWR_CTRL2_KFC 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLKSTOP_CTRL_KFC 0x1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define INTR_SPREAD_ENABLE_KFC 0x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CMU_KFC_SPARE0 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CMU_KFC_SPARE1 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CMU_KFC_SPARE2 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CMU_KFC_SPARE3 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CMU_KFC_SPARE4 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *Registers for CMU_MFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MUX_SEL_MFC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MUX_ENABLE_MFC 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MUX_STAT_MFC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DIV_MFC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DIV_STAT_MFC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define EN_ACLK_MFC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EN_ACLK_SECURE_SMMU2_MFC 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define EN_PCLK_MFC 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define EN_PCLK_SECURE_SMMU2_MFC 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define EN_IP_MFC 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *Registers for CMU_MIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MEM_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BUS_PLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MEDIA_PLL_LOCK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MEM_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MEM_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MEM_PLL_FDET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BUS_PLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BUS_PLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BUS_PLL_FDET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MEDIA_PLL_CON0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MEDIA_PLL_CON1 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MEDIA_PLL_FDET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MUX_SEL_MIF 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MUX_ENABLE_MIF 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MUX_STAT_MIF 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MUX_IGNORE_MIF 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DIV_MIF 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIV_MIF_PLL_FDET 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DIV_STAT_MIF 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DIV_STAT_MIF_PLL_FDET 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define EN_ACLK_MIF 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define EN_ACLK_MIF_SECURE_INTMEM 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EN_PCLK_MIF 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define EN_PCLK_MIF_SECURE_MONOCNT 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define EN_SCLK_MIF 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EN_IP_MIF 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define EN_IP_MIF_SECURE_MONOCNT 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define EN_IP_MIF_SECURE_INTEMEM 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DREX_FREQ_CTRL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PAUSE 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DDRPHY_LOCK_CTRL 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLKOUT_CMU_MIF 0xcb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *Registers for CMU_PERI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MUX_SEL_PERI 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MUX_SEL_PERI1 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MUX_ENABLE_PERI 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MUX_ENABLE_PERI1 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MUX_STAT_PERI 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MUX_STAT_PERI1 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MUX_IGNORE_PERI 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MUX_IGNORE_PERI1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DIV_PERI 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DIV_STAT_PERI 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EN_PCLK_PERI0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EN_PCLK_PERI1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EN_PCLK_PERI2 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define EN_PCLK_PERI3 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define EN_PCLK_PERI_SECURE_CHIPID 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define EN_PCLK_PERI_SECURE_SECKEY 0x081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EN_PCLK_PERI_SECURE_TZPC 0x0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define EN_SCLK_PERI 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define EN_IP_PERI0 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define EN_IP_PERI1 0x0b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define EN_IP_PERI2 0x0b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EN_IP_PERI_SECURE_CHIPID 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EN_IP_PERI_SECURE_PROVKEY0 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define EN_IP_PERI_SECURE_PROVKEY1 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define EN_IP_PERI_SECURE_SECKEY 0x0b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EN_IP_PERI_SECURE_TOP_RTC 0x0b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EN_IP_PERI_SECURE_TZPC 0x0b24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *Registers for CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DISP_PLL_LOCK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define AUD_PLL_LOCK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DISP_PLL_CON0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DISP_PLL_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DISP_PLL_FDET 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define AUD_PLL_CON0 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AUD_PLL_CON1 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AUD_PLL_CON2 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AUD_PLL_FDET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MUX_SEL_TOP_PLL0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MUX_SEL_TOP_MFC 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MUX_SEL_TOP_G2D 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MUX_SEL_TOP_GSCL 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MUX_SEL_TOP_ISP10 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MUX_SEL_TOP_ISP11 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MUX_SEL_TOP_DISP0 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MUX_SEL_TOP_DISP1 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MUX_SEL_TOP_BUS 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MUX_SEL_TOP_PERI0 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MUX_SEL_TOP_PERI1 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MUX_SEL_TOP_FSYS 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MUX_ENABLE_TOP_PLL0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MUX_ENABLE_TOP_MFC 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MUX_ENABLE_TOP_G2D 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MUX_ENABLE_TOP_GSCL 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MUX_ENABLE_TOP_ISP10 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MUX_ENABLE_TOP_ISP11 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MUX_ENABLE_TOP_DISP0 0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MUX_ENABLE_TOP_DISP1 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MUX_ENABLE_TOP_BUS 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MUX_ENABLE_TOP_PERI0 0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MUX_ENABLE_TOP_PERI1 0x032c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MUX_ENABLE_TOP_FSYS 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MUX_STAT_TOP_PLL0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MUX_STAT_TOP_MFC 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MUX_STAT_TOP_G2D 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MUX_STAT_TOP_GSCL 0x040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MUX_STAT_TOP_ISP10 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MUX_STAT_TOP_ISP11 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MUX_STAT_TOP_DISP0 0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MUX_STAT_TOP_DISP1 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MUX_STAT_TOP_BUS 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MUX_STAT_TOP_PERI0 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MUX_STAT_TOP_PERI1 0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MUX_STAT_TOP_FSYS 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MUX_IGNORE_TOP_PLL0 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MUX_IGNORE_TOP_MFC 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MUX_IGNORE_TOP_G2D 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MUX_IGNORE_TOP_GSCL 0x050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MUX_IGNORE_TOP_ISP10 0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MUX_IGNORE_TOP_ISP11 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MUX_IGNORE_TOP_DISP0 0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MUX_IGNORE_TOP_DISP1 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MUX_IGNORE_TOP_BUS 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MUX_IGNORE_TOP_PERI0 0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MUX_IGNORE_TOP_PERI1 0x052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MUX_IGNORE_TOP_FSYS 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DIV_TOP_G2D_MFC 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DIV_TOP_GSCL_ISP0 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DIV_TOP_ISP10 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define DIV_TOP_ISP11 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DIV_TOP_DISP 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define DIV_TOP_BUS 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define DIV_TOP_PERI0 0x0618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DIV_TOP_PERI1 0x061c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define DIV_TOP_PERI2 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define DIV_TOP_FSYS0 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define DIV_TOP_FSYS1 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define DIV_TOP_HPM 0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DIV_TOP_PLL_FDET 0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DIV_STAT_TOP_G2D_MFC 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DIV_STAT_TOP_GSCL_ISP0 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DIV_STAT_TOP_ISP10 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define DIV_STAT_TOP_ISP11 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DIV_STAT_TOP_DISP 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DIV_STAT_TOP_BUS 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define DIV_STAT_TOP_PERI0 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define DIV_STAT_TOP_PERI1 0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DIV_STAT_TOP_PERI2 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define DIV_STAT_TOP_FSYS0 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DIV_STAT_TOP_FSYS1 0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DIV_STAT_TOP_HPM 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DIV_STAT_TOP_PLL_FDET 0x0730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define EN_ACLK_TOP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define EN_SCLK_TOP 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define EN_IP_TOP 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CLKOUT_CMU_TOP 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CLKOUT_CMU_TOP_DIV_STAT 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #endif /*__CLK_EXYNOS5260_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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