^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Rahul Sharma <rahul.sharma@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for Exynos5260 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-exynos5260.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/exynos5260-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Applicable for all 2550 Type PLLS for Exynos5260, listed below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Applicable for 2650 Type PLL for AUD_PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* CMU_AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const unsigned long aud_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MUX_SEL_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DIV_AUD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DIV_AUD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EN_ACLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) EN_PCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EN_SCLK_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EN_IP_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MUX_SEL_AUD, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_SEL_AUD, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MUX_SEL_AUD, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct samsung_div_clock aud_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DIV_AUD0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DIV_AUD1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DIV_AUD1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DIV_AUD1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EN_IP_AUD, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EN_IP_AUD, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct samsung_cmu_info aud_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .mux_clks = aud_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .div_clks = aud_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .nr_div_clks = ARRAY_SIZE(aud_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .gate_clks = aud_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .nr_clk_ids = AUD_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .clk_regs = aud_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void __init exynos5260_clk_aud_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) samsung_cmu_register_one(np, &aud_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) exynos5260_clk_aud_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* CMU_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned long disp_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_SEL_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_SEL_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MUX_SEL_DISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MUX_SEL_DISP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MUX_SEL_DISP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DIV_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) EN_ACLK_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) EN_PCLK_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EN_SCLK_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) EN_SCLK_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EN_IP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EN_IP_DISP_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "phyclk_dptx_phy_ch3_txd_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "phyclk_dptx_phy_ch2_txd_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "phyclk_dptx_phy_ch1_txd_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "phyclk_dptx_phy_ch0_txd_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "phyclk_hdmi_phy_tmds_clko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "phyclk_hdmi_phy_ref_clko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "phyclk_hdmi_phy_pixel_clko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "phyclk_hdmi_link_o_tmds_clkhi"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "phyclk_dptx_phy_o_ref_clk_24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "phyclk_dptx_phy_clk_div2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "mout_aclk_disp_222_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "phyclk_mipi_dphy_4l_m_rxclkesc0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mout_aclk_disp_333_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MUX_SEL_DISP0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mout_sclk_disp_pixel_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MUX_SEL_DISP0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mout_aclk_disp_222_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MUX_SEL_DISP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "mout_phyclk_dptx_phy_ch0_txd_clk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX_SEL_DISP0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "mout_phyclk_dptx_phy_ch1_txd_clk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX_SEL_DISP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "mout_phyclk_dptx_phy_ch2_txd_clk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX_SEL_DISP0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "mout_phyclk_dptx_phy_ch3_txd_clk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX_SEL_DISP0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "mout_phyclk_dptx_phy_clk_div2_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mout_phyclk_dptx_phy_clk_div2_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX_SEL_DISP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MUX_SEL_DISP1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX_SEL_DISP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MUX_SEL_DISP1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MUX(DISP_MOUT_HDMI_PHY_PIXEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "mout_phyclk_hdmi_phy_pixel_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mout_phyclk_hdmi_phy_pixel_clko_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX_SEL_DISP1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "mout_phyclk_hdmi_phy_ref_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mout_phyclk_hdmi_phy_ref_clko_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX_SEL_DISP1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "mout_phyclk_hdmi_phy_tmds_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mout_phyclk_hdmi_phy_tmds_clko_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX_SEL_DISP1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_SEL_DISP2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mout_sclk_hdmi_pixel_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX_SEL_DISP2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mout_sclk_hdmi_spdif_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MUX_SEL_DISP4, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct samsung_div_clock disp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DIV_DISP, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "mout_sclk_disp_pixel_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DIV_DISP, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "dout_sclk_hdmi_phy_pixel_clki",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "mout_sclk_hdmi_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DIV_DISP, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "mout_phyclk_hdmi_phy_pixel_clko_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "dout_sclk_hdmi_phy_pixel_clki",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EN_IP_DISP, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EN_IP_DISP, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) EN_IP_DISP, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EN_IP_DISP, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EN_IP_DISP, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EN_IP_DISP, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EN_IP_DISP, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EN_IP_DISP, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) EN_IP_DISP, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EN_IP_DISP, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) EN_IP_DISP, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct samsung_cmu_info disp_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .mux_clks = disp_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .div_clks = disp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .nr_div_clks = ARRAY_SIZE(disp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .gate_clks = disp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .nr_clk_ids = DISP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .clk_regs = disp_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void __init exynos5260_clk_disp_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) samsung_cmu_register_one(np, &disp_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) exynos5260_clk_disp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* CMU_EGL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned long egl_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EGL_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) EGL_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) EGL_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) EGL_PLL_FREQ_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MUX_SEL_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MUX_ENABLE_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DIV_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DIV_EGL_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EN_ACLK_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EN_PCLK_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EN_SCLK_EGL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MUX_SEL_EGL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct samsung_div_clock egl_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DIV_EGL, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DIV_EGL, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) EGL_PLL_LOCK, EGL_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct samsung_cmu_info egl_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .pll_clks = egl_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .nr_pll_clks = ARRAY_SIZE(egl_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .mux_clks = egl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .div_clks = egl_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .nr_div_clks = ARRAY_SIZE(egl_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .nr_clk_ids = EGL_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clk_regs = egl_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void __init exynos5260_clk_egl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) samsung_cmu_register_one(np, &egl_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) exynos5260_clk_egl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* CMU_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const unsigned long fsys_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MUX_SEL_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MUX_SEL_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EN_ACLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) EN_ACLK_FSYS_SECURE_RTIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EN_ACLK_FSYS_SECURE_SMMU_RTIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) EN_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) EN_IP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) EN_IP_FSYS_SECURE_RTIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) EN_IP_FSYS_SECURE_SMMU_RTIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "phyclk_usbhost20_phy_phyclock"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "phyclk_usbhost20_phy_freeclk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "phyclk_usbhost20_phy_clk48mohci"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "phyclk_usbdrd30_udrd30_pipe_pclk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "phyclk_usbdrd30_udrd30_phyclock"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "mout_phyclk_usbdrd30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mout_phyclk_usbdrd30_phyclock_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MUX_SEL_FSYS1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "mout_phyclk_usbdrd30_pipe_pclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mout_phyclk_usbdrd30_pipe_pclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MUX_SEL_FSYS1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "mout_phyclk_usbhost20_clk48mohci_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mout_phyclk_usbhost20_clk48mohci_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MUX_SEL_FSYS1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "mout_phyclk_usbhost20_freeclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mout_phyclk_usbhost20_freeclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MUX_SEL_FSYS1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "mout_phyclk_usbhost20_phyclk_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mout_phyclk_usbhost20_phyclk_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MUX_SEL_FSYS1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "mout_phyclk_usbdrd30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) EN_SCLK_FSYS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "mout_phyclk_usbdrd30_phyclock_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) EN_SCLK_FSYS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) EN_IP_FSYS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) EN_IP_FSYS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) EN_IP_FSYS, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) EN_IP_FSYS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) EN_IP_FSYS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) EN_IP_FSYS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) EN_IP_FSYS, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) EN_IP_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) EN_IP_FSYS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct samsung_cmu_info fsys_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .mux_clks = fsys_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .gate_clks = fsys_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .nr_clk_ids = FSYS_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .clk_regs = fsys_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void __init exynos5260_clk_fsys_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) samsung_cmu_register_one(np, &fsys_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) exynos5260_clk_fsys_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* CMU_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned long g2d_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX_SEL_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MUX_STAT_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DIV_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EN_ACLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) EN_ACLK_G2D_SECURE_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) EN_ACLK_G2D_SECURE_SLIM_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) EN_ACLK_G2D_SECURE_SMMU_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) EN_ACLK_G2D_SECURE_SMMU_MDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EN_ACLK_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) EN_PCLK_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EN_PCLK_G2D_SECURE_SMMU_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) EN_PCLK_G2D_SECURE_SMMU_MDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) EN_PCLK_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) EN_IP_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) EN_IP_G2D_SECURE_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) EN_IP_G2D_SECURE_SLIM_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EN_IP_G2D_SECURE_SMMU_SSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EN_IP_G2D_SECURE_SMMU_MDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) EN_IP_G2D_SECURE_SMMU_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mout_aclk_g2d_333_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MUX_SEL_G2D, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct samsung_div_clock g2d_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DIV_G2D, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) EN_IP_G2D, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) EN_IP_G2D, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) EN_IP_G2D, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EN_IP_G2D, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) EN_IP_G2D_SECURE_SSS, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const struct samsung_cmu_info g2d_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .mux_clks = g2d_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .div_clks = g2d_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .gate_clks = g2d_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .nr_clk_ids = G2D_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .clk_regs = g2d_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void __init exynos5260_clk_g2d_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) samsung_cmu_register_one(np, &g2d_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) exynos5260_clk_g2d_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* CMU_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const unsigned long g3d_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) G3D_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) G3D_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) G3D_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) G3D_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MUX_SEL_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DIV_G3D_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) EN_ACLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) EN_PCLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) EN_SCLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) EN_IP_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MUX_SEL_G3D, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct samsung_div_clock g3d_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) EN_IP_G3D, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) G3D_PLL_LOCK, G3D_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct samsung_cmu_info g3d_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pll_clks = g3d_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .mux_clks = g3d_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .div_clks = g3d_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .gate_clks = g3d_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .nr_clk_ids = G3D_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .clk_regs = g3d_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void __init exynos5260_clk_g3d_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) samsung_cmu_register_one(np, &g3d_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) exynos5260_clk_g3d_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* CMU_GSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const unsigned long gscl_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MUX_SEL_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DIV_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) EN_ACLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EN_ACLK_GSCL_FIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) EN_PCLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) EN_PCLK_GSCL_FIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) EN_SCLK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) EN_SCLK_GSCL_FIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) EN_IP_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) EN_IP_GSCL_FIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) EN_IP_GSCL_SECURE_SMMU_GSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) EN_IP_GSCL_SECURE_SMMU_GSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) EN_IP_GSCL_SECURE_SMMU_MSCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) EN_IP_GSCL_SECURE_SMMU_MSCL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mout_aclk_gscl_333_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MUX_SEL_GSCL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mout_aclk_m2m_400_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MUX_SEL_GSCL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) mout_aclk_gscl_fimc_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) MUX_SEL_GSCL, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MUX_SEL_GSCL, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const struct samsung_div_clock gscl_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "mout_aclk_m2m_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) DIV_GSCL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "mout_aclk_m2m_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) DIV_GSCL, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) EN_IP_GSCL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) EN_IP_GSCL, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) EN_IP_GSCL, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) EN_IP_GSCL, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) EN_IP_GSCL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) EN_IP_GSCL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) EN_IP_GSCL_FIMC, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) EN_IP_GSCL_FIMC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) EN_IP_GSCL_FIMC, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) EN_IP_GSCL_FIMC, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) EN_IP_GSCL_FIMC, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) EN_IP_GSCL_FIMC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) EN_IP_GSCL_FIMC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "mout_aclk_gscl_fimc_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) EN_IP_GSCL_FIMC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "mout_aclk_m2m_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "mout_aclk_m2m_400_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct samsung_cmu_info gscl_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .mux_clks = gscl_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .div_clks = gscl_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .nr_div_clks = ARRAY_SIZE(gscl_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .gate_clks = gscl_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .nr_clk_ids = GSCL_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .clk_regs = gscl_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static void __init exynos5260_clk_gscl_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) samsung_cmu_register_one(np, &gscl_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) exynos5260_clk_gscl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* CMU_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const unsigned long isp_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MUX_SEL_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) MUX_SEL_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DIV_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) EN_ACLK_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) EN_ACLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) EN_PCLK_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) EN_PCLK_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) EN_SCLK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) EN_IP_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) EN_IP_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MUX_SEL_ISP0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MUX_SEL_ISP0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct samsung_div_clock isp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DIV_ISP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DIV_ISP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DIV_ISP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) DIV_ISP, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) EN_IP_ISP0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) EN_IP_ISP1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) EN_IP_ISP1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) EN_IP_ISP1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) EN_IP_ISP1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) EN_IP_ISP1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) EN_IP_ISP1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) EN_IP_ISP1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) EN_IP_ISP1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) EN_IP_ISP1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) EN_IP_ISP1, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) EN_IP_ISP1, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) EN_IP_ISP1, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) EN_IP_ISP1, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) EN_IP_ISP1, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) EN_IP_ISP1, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) EN_IP_ISP1, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) EN_IP_ISP1, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) EN_IP_ISP1, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) EN_IP_ISP1, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) EN_IP_ISP1, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) EN_IP_ISP1, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) EN_IP_ISP1, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const struct samsung_cmu_info isp_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .mux_clks = isp_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .div_clks = isp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .nr_div_clks = ARRAY_SIZE(isp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .gate_clks = isp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .nr_clk_ids = ISP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .clk_regs = isp_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void __init exynos5260_clk_isp_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) samsung_cmu_register_one(np, &isp_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) exynos5260_clk_isp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* CMU_KFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const unsigned long kfc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) KFC_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) KFC_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) KFC_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) KFC_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MUX_SEL_KFC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MUX_SEL_KFC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DIV_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DIV_KFC_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) EN_ACLK_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) EN_PCLK_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) EN_SCLK_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) EN_IP_KFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MUX_SEL_KFC0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct samsung_div_clock kfc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DIV_KFC, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) KFC_PLL_LOCK, KFC_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct samsung_cmu_info kfc_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .pll_clks = kfc_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .nr_pll_clks = ARRAY_SIZE(kfc_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .mux_clks = kfc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .div_clks = kfc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .nr_div_clks = ARRAY_SIZE(kfc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .nr_clk_ids = KFC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .clk_regs = kfc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static void __init exynos5260_clk_kfc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) samsung_cmu_register_one(np, &kfc_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) exynos5260_clk_kfc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* CMU_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned long mfc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MUX_SEL_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DIV_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) EN_ACLK_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) EN_ACLK_SECURE_SMMU2_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) EN_PCLK_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) EN_PCLK_SECURE_SMMU2_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) EN_IP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) EN_IP_MFC_SECURE_SMMU2_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) mout_aclk_mfc_333_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) MUX_SEL_MFC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const struct samsung_div_clock mfc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DIV_MFC, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) EN_IP_MFC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const struct samsung_cmu_info mfc_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .mux_clks = mfc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .div_clks = mfc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .gate_clks = mfc_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .nr_clk_ids = MFC_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .clk_regs = mfc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static void __init exynos5260_clk_mfc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) samsung_cmu_register_one(np, &mfc_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) exynos5260_clk_mfc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* CMU_MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const unsigned long mif_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MEM_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) BUS_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) MEDIA_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) MEM_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) MEM_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) MEM_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) BUS_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) BUS_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) BUS_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MEDIA_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) MEDIA_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MEDIA_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MUX_SEL_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) DIV_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) DIV_MIF_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) EN_ACLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) EN_ACLK_MIF_SECURE_DREX1_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) EN_ACLK_MIF_SECURE_DREX0_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) EN_ACLK_MIF_SECURE_INTMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) EN_PCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) EN_PCLK_MIF_SECURE_MONOCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) EN_PCLK_MIF_SECURE_RTC_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) EN_PCLK_MIF_SECURE_DREX1_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) EN_PCLK_MIF_SECURE_DREX0_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) EN_SCLK_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) EN_IP_MIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) EN_IP_MIF_SECURE_MONOCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) EN_IP_MIF_SECURE_RTC_APBIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) EN_IP_MIF_SECURE_DREX1_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) EN_IP_MIF_SECURE_DREX0_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) EN_IP_MIF_SECURE_INTEMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MUX_SEL_MIF, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) MUX_SEL_MIF, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) MUX_SEL_MIF, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) MUX_SEL_MIF, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) MUX_SEL_MIF, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MUX_SEL_MIF, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) MUX_SEL_MIF, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct samsung_div_clock mif_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) DIV_MIF, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) DIV_MIF, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) DIV_MIF, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) DIV_MIF, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) DIV_MIF, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) DIV_MIF, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) DIV_MIF, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) DIV_MIF, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) EN_IP_MIF_SECURE_MONOCNT, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) EN_IP_MIF_SECURE_RTC_APBIF, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) EN_IP_MIF_SECURE_DREX1_TZ, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) EN_IP_MIF_SECURE_DREX0_TZ, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) EN_IP_MIF_SECURE_INTEMEM, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) "dout_clkm_phy", EN_SCLK_MIF, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "dout_clkm_phy", EN_SCLK_MIF, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) MEM_PLL_LOCK, MEM_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) BUS_PLL_LOCK, BUS_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const struct samsung_cmu_info mif_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .pll_clks = mif_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .mux_clks = mif_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .div_clks = mif_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .nr_div_clks = ARRAY_SIZE(mif_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .gate_clks = mif_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .nr_clk_ids = MIF_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .clk_regs = mif_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static void __init exynos5260_clk_mif_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) samsung_cmu_register_one(np, &mif_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) exynos5260_clk_mif_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* CMU_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static const unsigned long peri_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) MUX_SEL_PERI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MUX_SEL_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) DIV_PERI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) EN_PCLK_PERI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) EN_PCLK_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) EN_PCLK_PERI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) EN_PCLK_PERI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) EN_PCLK_PERI_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) EN_PCLK_PERI_SECURE_PROVKEY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) EN_PCLK_PERI_SECURE_PROVKEY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) EN_PCLK_PERI_SECURE_SECKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) EN_PCLK_PERI_SECURE_ANTIRBKCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) EN_PCLK_PERI_SECURE_TOP_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) EN_PCLK_PERI_SECURE_TZPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) EN_SCLK_PERI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) EN_SCLK_PERI_SECURE_TOP_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) EN_IP_PERI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) EN_IP_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) EN_IP_PERI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) EN_IP_PERI_SECURE_CHIPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) EN_IP_PERI_SECURE_PROVKEY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) EN_IP_PERI_SECURE_PROVKEY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) EN_IP_PERI_SECURE_SECKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) EN_IP_PERI_SECURE_ANTIRBKCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) EN_IP_PERI_SECURE_TOP_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) EN_IP_PERI_SECURE_TZPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) "phyclk_hdmi_phy_ref_cko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) "phyclk_hdmi_phy_ref_cko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MUX_SEL_PERI1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) MUX_SEL_PERI1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) MUX_SEL_PERI1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct samsung_div_clock peri_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) EN_IP_PERI0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) EN_IP_PERI0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) EN_IP_PERI0, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) EN_IP_PERI0, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) EN_IP_PERI0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) EN_IP_PERI0, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) EN_IP_PERI0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) EN_IP_PERI0, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) EN_IP_PERI0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) EN_IP_PERI0, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) EN_IP_PERI0, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) EN_IP_PERI0, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) EN_IP_PERI0, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) EN_IP_PERI0, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) EN_IP_PERI0, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) EN_IP_PERI0, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) EN_IP_PERI0, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) EN_IP_PERI0, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) EN_IP_PERI0, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) EN_IP_PERI0, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) EN_IP_PERI0, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) EN_IP_PERI2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) EN_IP_PERI2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) EN_IP_PERI2, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) EN_IP_PERI2, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) EN_IP_PERI2, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) EN_IP_PERI2, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) EN_IP_PERI2, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) EN_IP_PERI2, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) EN_IP_PERI2, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) EN_IP_PERI2, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) EN_IP_PERI2, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) EN_IP_PERI2, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) EN_IP_PERI2, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) EN_IP_PERI2, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) EN_IP_PERI2, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static const struct samsung_cmu_info peri_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .mux_clks = peri_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .div_clks = peri_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .nr_div_clks = ARRAY_SIZE(peri_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .gate_clks = peri_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .nr_clk_ids = PERI_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .clk_regs = peri_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static void __init exynos5260_clk_peri_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) samsung_cmu_register_one(np, &peri_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) exynos5260_clk_peri_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* CMU_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const unsigned long top_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) DISP_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) AUD_PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) DISP_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) DISP_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) DISP_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) AUD_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) AUD_PLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) AUD_PLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) AUD_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) MUX_SEL_TOP_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) MUX_SEL_TOP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) MUX_SEL_TOP_G2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) MUX_SEL_TOP_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) MUX_SEL_TOP_ISP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) MUX_SEL_TOP_ISP11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) MUX_SEL_TOP_DISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) MUX_SEL_TOP_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) MUX_SEL_TOP_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) MUX_SEL_TOP_PERI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) MUX_SEL_TOP_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) MUX_SEL_TOP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) DIV_TOP_G2D_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) DIV_TOP_GSCL_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) DIV_TOP_ISP10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) DIV_TOP_ISP11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) DIV_TOP_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) DIV_TOP_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) DIV_TOP_PERI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) DIV_TOP_PERI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) DIV_TOP_PERI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) DIV_TOP_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) DIV_TOP_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) DIV_TOP_HPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) DIV_TOP_PLL_FDET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) EN_ACLK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) EN_SCLK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) EN_IP_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* fixed rate clocks generated inside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) 0, 270000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) 0, 270000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) 0, 270000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) 0, 270000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) 0, 250000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) 0, 1660000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) NULL, 0, 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) 0, 187500000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) 0, 135000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) "mout_gscl_bustop_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) "mout_m2m_mediatop_400"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) "mout_gscl_bustop_fimc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) "mout_memtop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) "mout_mediatop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) "mout_mediatop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) "mout_mediatop_pll_user"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const struct samsung_mux_clock top_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mout_mediatop_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) MUX_SEL_TOP_PLL0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mout_memtop_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) MUX_SEL_TOP_PLL0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) mout_bustop_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) MUX_SEL_TOP_PLL0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) MUX_SEL_TOP_PLL0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) MUX_SEL_TOP_PLL0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) mout_audtop_pll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MUX_SEL_TOP_PLL0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) MUX_SEL_TOP_DISP0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MUX_SEL_TOP_DISP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) MUX_SEL_TOP_DISP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) MUX_SEL_TOP_DISP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) MUX_SEL_TOP_DISP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) mout_disp_media_pixel_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) MUX_SEL_TOP_DISP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mout_sclk_peri_spi_clk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MUX_SEL_TOP_PERI1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) mout_sclk_peri_spi_clk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MUX_SEL_TOP_PERI1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mout_sclk_peri_spi_clk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) MUX_SEL_TOP_PERI1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mout_sclk_peri_uart_uclk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) MUX_SEL_TOP_PERI1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) mout_sclk_peri_uart_uclk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) MUX_SEL_TOP_PERI1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) mout_sclk_peri_uart_uclk_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) MUX_SEL_TOP_PERI1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) mout_bus_bustop_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MUX_SEL_TOP_BUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) mout_bus_bustop_100_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) MUX_SEL_TOP_BUS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) mout_bus_bustop_100_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) MUX_SEL_TOP_BUS, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) mout_bus_bustop_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) MUX_SEL_TOP_BUS, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) mout_bus_bustop_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) MUX_SEL_TOP_BUS, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mout_bus_bustop_100_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MUX_SEL_TOP_BUS, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mout_bus_bustop_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) MUX_SEL_TOP_BUS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) mout_bus_bustop_100_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) MUX_SEL_TOP_BUS, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) mout_sclk_fsys_usb_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MUX_SEL_TOP_FSYS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mout_sclk_fsys_mmc_sdclkin_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) MUX_SEL_TOP_FSYS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mout_sclk_fsys_mmc2_sdclkin_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) MUX_SEL_TOP_FSYS, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) mout_sclk_fsys_mmc_sdclkin_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) MUX_SEL_TOP_FSYS, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) mout_sclk_fsys_mmc1_sdclkin_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) MUX_SEL_TOP_FSYS, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) mout_sclk_fsys_mmc_sdclkin_a_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) MUX_SEL_TOP_FSYS, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) mout_sclk_fsys_mmc0_sdclkin_b_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) MUX_SEL_TOP_FSYS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) mout_isp1_media_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) MUX_SEL_TOP_ISP10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) MUX_SEL_TOP_ISP10, 8 , 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) mout_isp1_media_266_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) MUX_SEL_TOP_ISP10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) MUX_SEL_TOP_ISP10, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) MUX_SEL_TOP_ISP11, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) MUX_SEL_TOP_ISP11, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) mout_sclk_isp_uart_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) MUX_SEL_TOP_ISP11, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) mout_sclk_isp_sensor_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) MUX_SEL_TOP_ISP11, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mout_sclk_isp_sensor_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) MUX_SEL_TOP_ISP11, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) mout_sclk_isp_sensor_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) MUX_SEL_TOP_ISP11, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) mout_mfc_bustop_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MUX_SEL_TOP_MFC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MUX_SEL_TOP_MFC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) mout_g2d_bustop_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) MUX_SEL_TOP_G2D, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MUX_SEL_TOP_G2D, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) mout_m2m_mediatop_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) MUX_SEL_TOP_GSCL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) mout_aclk_gscl_400_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) MUX_SEL_TOP_GSCL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) mout_gscl_bustop_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) MUX_SEL_TOP_GSCL, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) mout_aclk_gscl_333_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) MUX_SEL_TOP_GSCL, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) mout_gscl_bustop_fimc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) MUX_SEL_TOP_GSCL, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) mout_aclk_gscl_fimc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) MUX_SEL_TOP_GSCL, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static const struct samsung_div_clock top_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) DIV_TOP_G2D_MFC, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) DIV_TOP_G2D_MFC, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) DIV_TOP_GSCL_ISP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) DIV_TOP_GSCL_ISP0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) DIV_TOP_ISP10, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) DIV_TOP_ISP10, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) DIV_TOP_DISP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) DIV_TOP_DISP, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) DIV_TOP_PERI2, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "dout_sclk_fsys_usbdrd30_suspend_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) "mout_sclk_fsys_mmc0_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) DIV_TOP_FSYS0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) "dout_sclk_fsys_mmc0_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) DIV_TOP_FSYS0, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) "mout_sclk_fsys_mmc1_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) DIV_TOP_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) "dout_sclk_fsys_mmc1_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) DIV_TOP_FSYS1, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) "mout_sclk_fsys_mmc2_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) DIV_TOP_FSYS1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) "dout_sclk_fsys_mmc2_sdclkin_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) DIV_TOP_FSYS1, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static const struct samsung_gate_clock top_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) "dout_sclk_fsys_mmc0_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) "dout_sclk_fsys_mmc1_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) "dout_sclk_fsys_mmc2_sdclkin_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const struct samsung_pll_clock top_pll_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) DISP_PLL_LOCK, DISP_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) pll2550_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) AUD_PLL_LOCK, AUD_PLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) pll2650_24mhz_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static const struct samsung_cmu_info top_cmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .pll_clks = top_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .mux_clks = top_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .div_clks = top_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .nr_div_clks = ARRAY_SIZE(top_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .gate_clks = top_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .fixed_clks = fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .nr_clk_ids = TOP_NR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .clk_regs = top_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static void __init exynos5260_clk_top_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) samsung_cmu_register_one(np, &top_cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) exynos5260_clk_top_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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