^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Common Clock Framework support for Exynos5250 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/exynos5250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-exynos5-subcmu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define APLL_LOCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APLL_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRC_CPU 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DIV_CPU0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWR_CTRL1 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWR_CTRL2 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPLL_LOCK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPLL_CON0 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SRC_CORE1 0x4204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GATE_IP_ACP 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GATE_IP_ISP0 0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GATE_IP_ISP1 0xc804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPLL_LOCK 0x10020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EPLL_LOCK 0x10030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VPLL_LOCK 0x10040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPLL_LOCK 0x10050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPLL_CON0 0x10120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EPLL_CON0 0x10130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VPLL_CON0 0x10140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPLL_CON0 0x10150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRC_TOP0 0x10210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRC_TOP1 0x10214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_TOP2 0x10218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_TOP3 0x1021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_GSCL 0x10220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_DISP1_0 0x1022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SRC_MAU 0x10240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRC_FSYS 0x10244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRC_GEN 0x10248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRC_PERIC0 0x10250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRC_PERIC1 0x10254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRC_MASK_GSCL 0x10320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRC_MASK_DISP1_0 0x1032c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_MASK_MAU 0x10334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRC_MASK_FSYS 0x10340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_MASK_GEN 0x10344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRC_MASK_PERIC0 0x10350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRC_MASK_PERIC1 0x10354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DIV_TOP0 0x10510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DIV_TOP1 0x10514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DIV_GSCL 0x10520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DIV_DISP1_0 0x1052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DIV_GEN 0x1053c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DIV_MAU 0x10544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DIV_FSYS0 0x10548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DIV_FSYS1 0x1054c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DIV_FSYS2 0x10550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DIV_PERIC0 0x10558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DIV_PERIC1 0x1055c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DIV_PERIC2 0x10560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DIV_PERIC3 0x10564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DIV_PERIC4 0x10568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DIV_PERIC5 0x1056c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GATE_IP_GSCL 0x10920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GATE_IP_DISP1 0x10928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GATE_IP_MFC 0x1092c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GATE_IP_G3D 0x10930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GATE_IP_GEN 0x10934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GATE_IP_FSYS 0x10944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GATE_IP_PERIC 0x10950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GATE_IP_PERIS 0x10960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BPLL_LOCK 0x20010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BPLL_CON0 0x20110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SRC_CDREX 0x20200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLL_DIV2_SEL 0x20a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*Below definitions are used for PWR_CTRL settings*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PWR_CTRL2_DIV2_UP_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PWR_CTRL2_DIV1_UP_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* list of PLLs to be registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum exynos5250_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) apll, mpll, cpll, epll, vpll, gpll, bpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) nr_plls /* number of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const unsigned long exynos5250_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SRC_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DIV_CPU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PWR_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PWR_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SRC_CORE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SRC_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SRC_TOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SRC_TOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SRC_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SRC_DISP1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SRC_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SRC_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SRC_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SRC_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SRC_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SRC_MASK_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SRC_MASK_DISP1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SRC_MASK_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SRC_MASK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SRC_MASK_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SRC_MASK_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SRC_MASK_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DIV_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DIV_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DIV_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DIV_DISP1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DIV_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DIV_MAU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DIV_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DIV_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DIV_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DIV_PERIC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DIV_PERIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DIV_PERIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DIV_PERIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DIV_PERIC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DIV_PERIC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GATE_IP_GSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GATE_IP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GATE_IP_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GATE_IP_GEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GATE_IP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GATE_IP_PERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GATE_IP_PERIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SRC_CDREX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PLL_DIV2_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GATE_IP_DISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GATE_IP_ACP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GATE_IP_ISP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GATE_IP_ISP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "mout_aclk300_disp1_mid1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "mout_mpll_user", "mout_epll", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "mout_cpll", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "sclk_uhostphy", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "mout_mpll_user", "mout_epll", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "mout_cpll", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "sclk_uhostphy", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "mout_mpll_user", "mout_epll", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "mout_cpll", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "sclk_uhostphy", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "mout_mpll_user", "mout_epll", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "mout_cpll", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "none" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "spdif_extclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* fixed rate clocks generated outside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* fixed rate clocks generated inside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * NOTE: Following table is sorted by (clock domain, register address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * bitfield shift) triplet in ascending order. When adding new entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * please make sure that the order is kept, to avoid merge conflicts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * and make further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * CMU_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * CMU_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mout_aclk200_sub_p, SRC_TOP3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mout_aclk300_sub_p, SRC_TOP3, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SRC_TOP3, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * CMU_CDREX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * NOTE: Following table is sorted by (clock domain, register address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * bitfield shift) triplet in ascending order. When adding new entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * please make sure that the order is kept, to avoid merge conflicts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * and make further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * CMU_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DIV_F(0, "div_mipi1_pre", "div_mipi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DIV_F(0, "div_mmc_pre0", "div_mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DIV_F(0, "div_mmc_pre1", "div_mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DIV_F(0, "div_mmc_pre2", "div_mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DIV_F(0, "div_mmc_pre3", "div_mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DIV_F(0, "div_spi_pre0", "div_spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DIV_F(0, "div_spi_pre1", "div_spi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DIV_F(0, "div_spi_pre2", "div_spi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * NOTE: Following table is sorted by (clock domain, register address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * bitfield shift) triplet in ascending order. When adding new entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * please make sure that the order is kept, to avoid merge conflicts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * and make further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * CMU_ACP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * CMU_TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) SRC_MASK_DISP1_0, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SRC_MASK_PERIC1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE_IP_GSCL, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE_IP_GSCL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GATE_IP_GSCL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE_IP_GSCL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE_IP_GSCL, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE_IP_GSCL, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE_IP_GSCL, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE_IP_FSYS, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(CLK_SYSREG, "sysreg", "div_aclk66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE_IP_ISP0, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE_IP_ISP0, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE_IP_ISP0, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE_IP_ISP0, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE_IP_ISP0, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE_IP_ISP0, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE_IP_ISP1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE_IP_ISP1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE_IP_ISP1, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE_IP_ISP1, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GATE_IP_DISP1, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE_IP_DISP1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .gate_clks = exynos5250_disp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .suspend_regs = exynos5250_disp_suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .pd_name = "DISP1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &exynos5250_disp_subcmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* sorted in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* PLL_36XX_RATE(rate, m, p, s, k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Not in UM, but need for eDP on snow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* sorted in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* PLL_36XX_RATE(rate, m, p, s, k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* sorted in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* PLL_35XX_RATE(fin, rate, m, p, s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) MPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) BPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) CPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) VPLL_LOCK, VPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define E5250_CPU_DIV1(hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (((hpm) << 4) | (copy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct of_device_id ext_clk_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { .compatible = "samsung,clock-xxti", .data = (void *)0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* register exynox5250 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void __init exynos5250_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) panic("%s: unable to determine soc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ext_clk_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ARRAY_SIZE(exynos5250_pll_pmux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (_get_rate("fin_pll") == 24 * MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (_get_rate("mout_vpllsrc") == 24 * MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) samsung_clk_register_pll(ctx, exynos5250_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ARRAY_SIZE(exynos5250_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ARRAY_SIZE(exynos5250_fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ARRAY_SIZE(exynos5250_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) samsung_clk_register_mux(ctx, exynos5250_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ARRAY_SIZE(exynos5250_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) samsung_clk_register_div(ctx, exynos5250_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ARRAY_SIZE(exynos5250_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) samsung_clk_register_gate(ctx, exynos5250_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ARRAY_SIZE(exynos5250_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) CLK_CPU_HAS_DIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * Enable arm clock down (in idle) and set arm divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * ratios in WFI/WFE state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) __raw_writel(tmp, reg_base + PWR_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * Enable arm clock up (on exiting idle). Set arm divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * ratios when not in idle along with the standby duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * ratios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) __raw_writel(tmp, reg_base + PWR_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ARRAY_SIZE(exynos5250_clk_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) exynos5250_subcmus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) _get_rate("div_arm2"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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