^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __CLK_EXYNOS5_SUBCMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __CLK_EXYNOS5_SUBCMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) struct exynos5_subcmu_reg_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) u32 save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct exynos5_subcmu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) const struct samsung_div_clock *div_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned int nr_div_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) const struct samsung_gate_clock *gate_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned int nr_gate_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct exynos5_subcmu_reg_dump *suspend_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int nr_suspend_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const char *pd_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct exynos5_subcmu_info **cmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif