^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Marek Szyprowski <m.szyprowski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Common Clock Framework support for Exynos5 power-domain dependent clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk-exynos5-subcmu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct exynos5_subcmu_info **cmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int nr_cmus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void exynos5_subcmu_clk_save(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct exynos5_subcmu_reg_dump *rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int num_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) for (; num_regs > 0; --num_regs, ++rd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) rd->save = readl(base + rd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) rd->save &= rd->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void exynos5_subcmu_clk_restore(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct exynos5_subcmu_reg_dump *rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int num_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) for (; num_regs > 0; --num_regs, ++rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) writel((readl(base + rd->offset) & ~rd->mask) | rd->save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) base + rd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct samsung_gate_clock *list, int nr_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) while (nr_clk--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Pass the needed clock provider context and register sub-CMU clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * NOTE: This function has to be called from the main, OF_CLK_DECLARE-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * initialized clock provider driver. This happens very early during boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * process. Then this driver, during core_initcall registers two platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * driver and second, for handling its per-domain child-devices. Those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * platform drivers are bound to their devices a bit later in arch_initcall,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * when OF-core populates all device-tree nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const struct exynos5_subcmu_info **_cmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ctx = _ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cmu = _cmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) nr_cmus = _nr_cmus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) for (; _nr_cmus--; _cmu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (*_cmu)->nr_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (*_cmu)->nr_suspend_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int __maybe_unused exynos5_subcmu_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spin_lock_irqsave(&ctx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) info->nr_suspend_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_unlock_irqrestore(&ctx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int __maybe_unused exynos5_subcmu_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_lock_irqsave(&ctx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) info->nr_suspend_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spin_unlock_irqrestore(&ctx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int __init exynos5_subcmu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pm_runtime_set_suspended(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pm_runtime_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ctx->dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct dev_pm_ops exynos5_subcmu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SET_RUNTIME_PM_OPS(exynos5_subcmu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) exynos5_subcmu_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct platform_driver exynos5_subcmu_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "exynos5-subcmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .pm = &exynos5_subcmu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .probe = exynos5_subcmu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init exynos5_clk_register_subcmu(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct exynos5_subcmu_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device_node *pd_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct of_phandle_args genpdspec = { .np = pd_node };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pdev = platform_device_alloc("exynos5-subcmu", PLATFORM_DEVID_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pdev->dev.parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) platform_set_drvdata(pdev, (void *)info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) of_genpd_add_device(&genpdspec, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int __init exynos5_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (of_property_read_string(np, "label", &name) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < nr_cmus; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (strcmp(cmu[i]->pd_name, name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) exynos5_clk_register_subcmu(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cmu[i], np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct of_device_id exynos5_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .compatible = "samsung,exynos5250-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .compatible = "samsung,exynos5420-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .compatible = "samsung,exynos5800-clock", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver exynos5_clk_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "exynos5-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .of_match_table = exynos5_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .probe = exynos5_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init exynos5_clk_drv_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) platform_driver_register(&exynos5_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) platform_driver_register(&exynos5_subcmu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) core_initcall(exynos5_clk_drv_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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