^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Common Clock Framework support for all Exynos4 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/exynos4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Exynos4 clock controller register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRC_LEFTBUS 0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DIV_LEFTBUS 0x4500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GATE_IP_LEFTBUS 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define E4X12_GATE_IP_IMAGE 0x4930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKOUT_CMU_LEFTBUS 0x4a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRC_RIGHTBUS 0x8200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DIV_RIGHTBUS 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GATE_IP_RIGHTBUS 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define E4X12_GATE_IP_PERIR 0x8960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKOUT_CMU_RIGHTBUS 0x8a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EPLL_LOCK 0xc010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VPLL_LOCK 0xc020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EPLL_CON0 0xc110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EPLL_CON1 0xc114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EPLL_CON2 0xc118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VPLL_CON0 0xc120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VPLL_CON1 0xc124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VPLL_CON2 0xc128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRC_TOP0 0xc210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRC_TOP1 0xc214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_CAM 0xc220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_TV 0xc224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_MFC 0xc228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_G3D 0xc22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define E4210_SRC_IMAGE 0xc230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRC_LCD0 0xc234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define E4210_SRC_LCD1 0xc238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define E4X12_SRC_ISP 0xc238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRC_MAUDIO 0xc23c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRC_FSYS 0xc240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRC_PERIL0 0xc250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_PERIL1 0xc254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define E4X12_SRC_CAM1 0xc258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_MASK_TOP 0xc310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRC_MASK_CAM 0xc320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRC_MASK_TV 0xc324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRC_MASK_LCD0 0xc334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define E4210_SRC_MASK_LCD1 0xc338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define E4X12_SRC_MASK_ISP 0xc338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SRC_MASK_MAUDIO 0xc33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRC_MASK_FSYS 0xc340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SRC_MASK_PERIL0 0xc350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SRC_MASK_PERIL1 0xc354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DIV_TOP 0xc510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DIV_CAM 0xc520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DIV_TV 0xc524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DIV_MFC 0xc528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DIV_G3D 0xc52c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DIV_IMAGE 0xc530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DIV_LCD0 0xc534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define E4210_DIV_LCD1 0xc538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define E4X12_DIV_ISP 0xc538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DIV_MAUDIO 0xc53c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DIV_FSYS0 0xc540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DIV_FSYS1 0xc544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DIV_FSYS2 0xc548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DIV_FSYS3 0xc54c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DIV_PERIL0 0xc550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DIV_PERIL1 0xc554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DIV_PERIL2 0xc558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DIV_PERIL3 0xc55c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DIV_PERIL4 0xc560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DIV_PERIL5 0xc564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define E4X12_DIV_CAM1 0xc568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define E4X12_GATE_BUS_FSYS1 0xc744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GATE_SCLK_CAM 0xc820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GATE_IP_CAM 0xc920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GATE_IP_TV 0xc924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GATE_IP_MFC 0xc928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GATE_IP_G3D 0xc92c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define E4210_GATE_IP_IMAGE 0xc930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GATE_IP_LCD0 0xc934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define E4210_GATE_IP_LCD1 0xc938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define E4X12_GATE_IP_ISP 0xc938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define E4X12_GATE_IP_MAUDIO 0xc93c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GATE_IP_FSYS 0xc940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GATE_IP_GPS 0xc94c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GATE_IP_PERIL 0xc950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define E4210_GATE_IP_PERIR 0xc960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GATE_BLOCK 0xc970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLKOUT_CMU_TOP 0xca00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define E4X12_MPLL_LOCK 0x10008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define E4X12_MPLL_CON0 0x10108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SRC_DMC 0x10200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SRC_MASK_DMC 0x10300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DIV_DMC0 0x10500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DIV_DMC1 0x10504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GATE_IP_DMC 0x10900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLKOUT_CMU_DMC 0x10a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define APLL_LOCK 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define E4210_MPLL_LOCK 0x14008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define APLL_CON0 0x14100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define E4210_MPLL_CON0 0x14108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SRC_CPU 0x14200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DIV_CPU0 0x14500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DIV_CPU1 0x14504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GATE_SCLK_CPU 0x14800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GATE_IP_CPU 0x14900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKOUT_CMU_CPU 0x14a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PWR_CTRL1 0x15020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define E4X12_PWR_CTRL2 0x15024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Below definitions are used for PWR_CTRL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* the exynos4 soc type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum exynos4_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EXYNOS4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXYNOS4X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* list of PLLs to be registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum exynos4_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) apll, mpll, epll, vpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) nr_plls /* number of PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static enum exynos4_soc exynos4_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * list of controller registers to be saved and restored during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * suspend/resume cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const unsigned long exynos4210_clk_save[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) E4210_SRC_IMAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) E4210_SRC_LCD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) E4210_SRC_MASK_LCD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) E4210_DIV_LCD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) E4210_GATE_IP_IMAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) E4210_GATE_IP_LCD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) E4210_GATE_IP_PERIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) E4210_MPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PWR_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned long exynos4x12_clk_save[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) E4X12_GATE_IP_IMAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) E4X12_GATE_IP_PERIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) E4X12_SRC_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) E4X12_DIV_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) E4X12_DIV_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) E4X12_MPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PWR_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) E4X12_PWR_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned long exynos4_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) VPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) EPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) VPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) VPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SRC_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DIV_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GATE_IP_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SRC_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DIV_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) GATE_IP_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SRC_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SRC_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SRC_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SRC_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SRC_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SRC_LCD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SRC_MAUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SRC_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SRC_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SRC_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SRC_MASK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SRC_MASK_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SRC_MASK_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SRC_MASK_LCD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SRC_MASK_MAUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SRC_MASK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SRC_MASK_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SRC_MASK_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DIV_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DIV_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DIV_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DIV_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DIV_IMAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DIV_LCD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DIV_MAUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DIV_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DIV_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DIV_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DIV_FSYS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DIV_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DIV_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DIV_PERIL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DIV_PERIL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DIV_PERIL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DIV_PERIL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GATE_SCLK_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GATE_IP_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GATE_IP_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GATE_IP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GATE_IP_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GATE_IP_LCD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GATE_IP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GATE_IP_GPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GATE_IP_PERIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GATE_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SRC_MASK_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SRC_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DIV_DMC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DIV_DMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GATE_IP_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) APLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SRC_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DIV_CPU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DIV_CPU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GATE_SCLK_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GATE_IP_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CLKOUT_CMU_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CLKOUT_CMU_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CLKOUT_CMU_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CLKOUT_CMU_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CLKOUT_CMU_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct samsung_clk_reg_dump src_mask_suspend[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .offset = VPLL_CON0, .value = 0x80600302, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .offset = EPLL_CON0, .value = 0x806F0302, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { .offset = SRC_MASK_TOP, .value = 0x00000001, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .offset = SRC_MASK_CAM, .value = 0x11111111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .offset = SRC_MASK_TV, .value = 0x00000111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .offset = SRC_MASK_DMC, .value = 0x00010000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "spdif_extclk", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Exynos 4210-specific parent groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "sclk_usbphy0", "none", "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "sclk_mpll", "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "sclk_epll", "sclk_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "sclk_usbphy1", "sclk_hdmiphy", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "sclk_epll", "sclk_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "div_gdl", "div_gpl" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "div_gdr", "div_gpr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "aclk160", "aclk133", "aclk200", "aclk100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "sclk_mfc", "sclk_g3d", "sclk_g2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "s_rxbyteclkhs0_4l" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "div_dphy", "none", "div_pwi" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "none", "arm_clk_div_2", "div_corem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "div_corem1", "div_corem0", "div_atb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "div_periph", "div_pclk_dbg", "div_hpm" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Exynos 4x12-specific parent groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "none", "sclk_hdmiphy", "mout_mpll_user_t",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "sclk_usbphy0", "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "sclk_usbphy0", "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "sclk_usbphy0", "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "none", "sclk_hdmiphy", "sclk_mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "sclk_epll", "sclk_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "div_gdl", "div_gpl" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "div_gdr", "div_gpr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "sclk_usbphy0", "none", "sclk_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "aclk160", "aclk133", "aclk200", "aclk100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "rx_half_byte_clk_csis1", "div_jpeg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "sclk_pwm_isp", "sclk_spi0_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "sclk_spi1_isp", "sclk_uart_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "sclk_pcm0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "div_dmc", "div_dphy", "fout_mpll_div_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "arm_clk_div_2", "div_corem0", "div_corem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "div_cores", "div_atb", "div_periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "div_pclk_dbg", "div_hpm" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* fixed rate clocks generated outside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* fixed rate clocks generated inside the soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* list of mux clocks supported in all exynos4 soc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* list of mux clocks supported in exynos4210 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CLKOUT_CMU_LEFTBUS, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CLKOUT_CMU_RIGHTBUS, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* list of mux clocks supported in exynos4x12 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) CLKOUT_CMU_LEFTBUS, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) CLKOUT_CMU_RIGHTBUS, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SRC_CPU, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SRC_TOP1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SRC_TOP1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* list of divider clocks supported in all exynos4 soc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CLKOUT_CMU_LEFTBUS, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) CLKOUT_CMU_RIGHTBUS, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* list of divider clocks supported in exynos4210 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* list of divider clocks supported in exynos4x12 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) DIV_TOP, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* list of gate clocks supported in all exynos4 soc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* list of gate clocks supported in exynos4210 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) E4210_GATE_IP_IMAGE, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* list of gate clocks supported in exynos4x12 soc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) E4X12_GATE_IP_IMAGE, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) E4X12_GATE_IP_ISP, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) E4X12_GATE_IP_ISP, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) E4X12_GATE_IP_ISP, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) E4X12_GATE_IP_ISP, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * resides in chipid register space, outside of the clock controller memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * mapped space. So to determine the parent of fin_pll clock, the chipid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * controller is first remapped and the value of XOM[0] bit is read to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * determine the parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static unsigned long __init exynos4_get_xom(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned long xom = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) void __iomem *chipid_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) chipid_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (chipid_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) xom = readl(chipid_base + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) iounmap(chipid_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return xom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct samsung_fixed_rate_clock fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned long finpll_f = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned int xom = exynos4_get_xom();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) parent_name = xom & 1 ? "xusbxti" : "xxti";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) clk = clk_get(NULL, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pr_err("%s: failed to lookup parent clock %s, assuming "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "fin_pll clock frequency is 24MHz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) finpll_f = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) fclk.id = CLK_FIN_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) fclk.name = "fin_pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) fclk.parent_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fclk.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) fclk.fixed_rate = finpll_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) samsung_clk_register_fixed_rate(ctx, &fclk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static const struct of_device_id ext_clk_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { .compatible = "samsung,clock-xxti", .data = (void *)0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* PLLs PMS values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) APLL_LOCK, APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) EPLL_LOCK, EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) VPLL_LOCK, VPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) APLL_LOCK, APLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) EPLL_LOCK, EPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) VPLL_LOCK, VPLL_CON0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void __init exynos4x12_core_down_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * Enable arm clock down (in idle) and set arm divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * ratios in WFI/WFE state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* On Exynos4412 enable it also on core 2 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (num_possible_cpus() == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) writel_relaxed(tmp, reg_base + PWR_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * Disable the clock up feature in case it was enabled by bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define E4210_CPU_DIV1(hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (((hpm) << 4) | ((copy) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define E4412_CPU_DIV1(cores, hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* register exynos4 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static void __init exynos4_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) enum exynos4_soc soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) exynos4_soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) panic("%s: failed to map registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ext_clk_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) exynos4_clk_register_finpll(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (exynos4_soc == EXYNOS4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) samsung_clk_register_mux(ctx, exynos4210_mux_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ARRAY_SIZE(exynos4210_mux_early));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (_get_rate("fin_pll") == 24000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) exynos4210_plls[apll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) exynos4210_apll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) exynos4210_plls[epll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) exynos4210_epll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (_get_rate("mout_vpllsrc") == 24000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) exynos4210_plls[vpll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) exynos4210_vpll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) samsung_clk_register_pll(ctx, exynos4210_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ARRAY_SIZE(exynos4210_plls), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (_get_rate("fin_pll") == 24000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) exynos4x12_plls[apll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) exynos4x12_apll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) exynos4x12_plls[epll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) exynos4x12_epll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) exynos4x12_plls[vpll].rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) exynos4x12_vpll_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) samsung_clk_register_pll(ctx, exynos4x12_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ARRAY_SIZE(exynos4x12_plls), reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ARRAY_SIZE(exynos4_fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) samsung_clk_register_mux(ctx, exynos4_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ARRAY_SIZE(exynos4_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) samsung_clk_register_div(ctx, exynos4_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ARRAY_SIZE(exynos4_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) samsung_clk_register_gate(ctx, exynos4_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ARRAY_SIZE(exynos4_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ARRAY_SIZE(exynos4_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (exynos4_soc == EXYNOS4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ARRAY_SIZE(exynos4210_fixed_rate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) samsung_clk_register_mux(ctx, exynos4210_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ARRAY_SIZE(exynos4210_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) samsung_clk_register_div(ctx, exynos4210_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ARRAY_SIZE(exynos4210_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) samsung_clk_register_gate(ctx, exynos4210_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ARRAY_SIZE(exynos4210_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) samsung_clk_register_fixed_factor(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) exynos4210_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ARRAY_SIZE(exynos4210_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ARRAY_SIZE(exynos4x12_mux_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) samsung_clk_register_div(ctx, exynos4x12_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ARRAY_SIZE(exynos4x12_div_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ARRAY_SIZE(exynos4x12_gate_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) samsung_clk_register_fixed_factor(ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) exynos4x12_fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ARRAY_SIZE(exynos4x12_fixed_factor_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (soc == EXYNOS4X12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) exynos4x12_core_down_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) samsung_clk_extended_sleep_init(reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (exynos4_soc == EXYNOS4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) samsung_clk_extended_sleep_init(reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ARRAY_SIZE(exynos4x12_clk_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) samsung_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) _get_rate("div_core2"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static void __init exynos4210_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) exynos4_clk_init(np, EXYNOS4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static void __init exynos4412_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) exynos4_clk_init(np, EXYNOS4X12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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