^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Common Clock Framework support for Exynos3250 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/exynos3250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRC_LEFTBUS 0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DIV_LEFTBUS 0x4500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GATE_IP_LEFTBUS 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRC_RIGHTBUS 0x8200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DIV_RIGHTBUS 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GATE_IP_RIGHTBUS 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GATE_IP_PERIR 0x8960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPLL_LOCK 0xc010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPLL_CON0 0xc110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VPLL_LOCK 0xc020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VPLL_CON0 0xc120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UPLL_LOCK 0xc030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UPLL_CON0 0xc130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SRC_TOP0 0xc210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SRC_TOP1 0xc214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SRC_CAM 0xc220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SRC_MFC 0xc228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SRC_G3D 0xc22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SRC_LCD 0xc234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SRC_ISP 0xc238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRC_FSYS 0xc240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRC_PERIL0 0xc250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_PERIL1 0xc254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_MASK_TOP 0xc310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_MASK_CAM 0xc320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_MASK_LCD 0xc334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SRC_MASK_ISP 0xc338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRC_MASK_FSYS 0xc340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRC_MASK_PERIL0 0xc350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRC_MASK_PERIL1 0xc354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DIV_TOP 0xc510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DIV_CAM 0xc520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DIV_MFC 0xc528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DIV_G3D 0xc52c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DIV_LCD 0xc534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DIV_ISP 0xc538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DIV_FSYS0 0xc540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DIV_FSYS1 0xc544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DIV_FSYS2 0xc548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DIV_PERIL0 0xc550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DIV_PERIL1 0xc554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DIV_PERIL3 0xc55c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DIV_PERIL4 0xc560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DIV_PERIL5 0xc564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DIV_CAM1 0xc568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKDIV2_RATIO 0xc580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GATE_SCLK_CAM 0xc820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GATE_SCLK_MFC 0xc828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GATE_SCLK_G3D 0xc82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GATE_SCLK_LCD 0xc834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GATE_SCLK_ISP_TOP 0xc838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GATE_SCLK_FSYS 0xc840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GATE_SCLK_PERIL 0xc850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GATE_IP_CAM 0xc920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GATE_IP_MFC 0xc928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GATE_IP_G3D 0xc92c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GATE_IP_LCD 0xc934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GATE_IP_ISP 0xc938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GATE_IP_FSYS 0xc940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GATE_IP_PERIL 0xc950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GATE_BLOCK 0xc970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define APLL_LOCK 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define APLL_CON0 0x14100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SRC_CPU 0x14200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DIV_CPU0 0x14500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DIV_CPU1 0x14504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PWR_CTRL1 0x15020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PWR_CTRL2 0x15024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Below definitions are used for PWR_CTRL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SRC_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DIV_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GATE_IP_LEFTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SRC_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DIV_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GATE_IP_RIGHTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GATE_IP_PERIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) VPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) VPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) UPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) UPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SRC_TOP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SRC_TOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SRC_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SRC_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SRC_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SRC_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SRC_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SRC_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SRC_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SRC_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SRC_MASK_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SRC_MASK_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SRC_MASK_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SRC_MASK_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SRC_MASK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SRC_MASK_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SRC_MASK_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DIV_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DIV_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DIV_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DIV_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DIV_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DIV_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DIV_FSYS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DIV_FSYS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DIV_FSYS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DIV_PERIL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DIV_PERIL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DIV_PERIL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DIV_PERIL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DIV_PERIL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DIV_CAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLKDIV2_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GATE_SCLK_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GATE_SCLK_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GATE_SCLK_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GATE_SCLK_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GATE_SCLK_ISP_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GATE_SCLK_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GATE_SCLK_PERIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GATE_IP_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GATE_IP_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GATE_IP_G3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GATE_IP_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GATE_IP_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GATE_IP_FSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GATE_IP_PERIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GATE_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) APLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SRC_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DIV_CPU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DIV_CPU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PWR_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PWR_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* list of all parent clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mout_vpllsrc_p) = { "fin_pll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PNAME(mout_aclk_400_mcuisp_sub_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) = { "fin_pll", "div_aclk_400_mcuisp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(group_sclk_p) = { "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "none", "none", "div_mpll_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "mout_epll_user", "mout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "div_mpll_pre", "mout_epll_user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "mout_vpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "none", "div_mpll_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "mout_epll_user", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "div_cam_blk_320", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "m_bitclkhsdiv4_2l", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "none", "none", "div_mpll_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "mout_epll_user", "mout_vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "none", "none", "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "div_lcd_blk_145", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct samsung_mux_clock mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* SRC_LEFTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SRC_LEFTBUS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* SRC_RIGHTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SRC_RIGHTBUS, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* SRC_TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* SRC_TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SRC_TOP1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* SRC_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* SRC_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* SRC_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* SRC_LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* SRC_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* SRC_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* SRC_PERIL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* SRC_PERIL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* SRC_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SRC_CPU, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct samsung_div_clock div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* DIV_LEFTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* DIV_RIGHTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* DIV_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* DIV_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* DIV_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* DIV_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* DIV_LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* DIV_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* DIV_FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* DIV_FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* DIV_FSYS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* DIV_PERIL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* DIV_PERIL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* DIV_PERIL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* DIV_PERIL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* DIV_CPU0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* DIV_CPU1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct samsung_gate_clock gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* GATE_IP_LEFTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* GATE_IP_RIGHTBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* GATE_IP_PERIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE_IP_PERIR, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* GATE_SCLK_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* GATE_SCLK_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* GATE_SCLK_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* GATE_SCLK_LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* GATE_SCLK_ISP_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* GATE_SCLK_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* GATE_SCLK_PERIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* GATE_IP_CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE_IP_CAM, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE_IP_CAM, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE_IP_CAM, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE_IP_CAM, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GATE_IP_CAM, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* GATE_IP_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* GATE_IP_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* GATE_IP_LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* GATE_IP_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE_IP_ISP, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE_IP_ISP, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE_IP_ISP, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* GATE_IP_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* GATE_IP_PERIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* APLL & MPLL & BPLL & UPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* EPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* VPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void __init exynos3_core_down_clock(void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Enable arm clock down (in idle) and set arm divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * ratios in WFI/WFE state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __raw_writel(tmp, reg_base + PWR_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Disable the clock up feature on Exynos4x12, in case it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * enabled by bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __raw_writel(0x0, reg_base + PWR_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct samsung_cmu_info cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .pll_clks = exynos3250_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .mux_clks = mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .nr_mux_clks = ARRAY_SIZE(mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .div_clks = div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .nr_div_clks = ARRAY_SIZE(div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .gate_clks = gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .nr_gate_clks = ARRAY_SIZE(gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .fixed_factor_clks = fixed_factor_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .nr_clk_ids = CLK_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .clk_regs = exynos3250_cmu_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ((corem) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define E3250_CPU_DIV1(hpm, copy) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) (((hpm) << 4) | ((copy) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static void __init exynos3250_cmu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct samsung_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ctx = samsung_cmu_register_one(np, &cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) hws = ctx->clk_data.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) CLK_CPU_HAS_DIV1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) exynos3_core_down_clock(ctx->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * CMU DMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define BPLL_LOCK 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define BPLL_CON0 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define BPLL_CON1 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define BPLL_CON2 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define SRC_DMC 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define DIV_DMC1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define GATE_BUS_DMC0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define GATE_BUS_DMC1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define GATE_BUS_DMC2 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define GATE_BUS_DMC3 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define GATE_SCLK_DMC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define GATE_IP_DMC0 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define GATE_IP_DMC1 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define EPLL_LOCK 0x1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define EPLL_CON0 0x1114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define EPLL_CON1 0x1118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define EPLL_CON2 0x111c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define SRC_EPLL 0x1120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) BPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) BPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) BPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) BPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) SRC_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DIV_DMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) GATE_BUS_DMC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE_BUS_DMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GATE_BUS_DMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE_BUS_DMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) GATE_SCLK_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE_IP_DMC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) GATE_IP_DMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) EPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) EPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) EPLL_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) EPLL_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SRC_EPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* SRC_DMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* SRC_EPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const struct samsung_div_clock dmc_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* DIV_DMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct samsung_cmu_info dmc_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .pll_clks = exynos3250_dmc_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .mux_clks = dmc_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .div_clks = dmc_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .nr_clk_ids = NR_CLKS_DMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .clk_regs = exynos3250_cmu_dmc_clk_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static void __init exynos3250_cmu_dmc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) samsung_cmu_register_one(np, &dmc_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) exynos3250_cmu_dmc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * CMU ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define DIV_ISP0 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define DIV_ISP1 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define GATE_IP_ISP0 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define GATE_IP_ISP1 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define GATE_SCLK_ISP 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct samsung_div_clock isp_div_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* DIV_ISP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* DIV_ISP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) DIV_ISP1, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) DIV_ISP1, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * NOTE: Following table is sorted by register address in ascending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * order and then bitfield shift in descending order, as it is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * in the User's Manual. When adding new entries, please make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * that the order is preserved, to avoid merge conflicts and make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * further work with defined data easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* GATE_IP_ISP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GATE(CLK_FD, "fd", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* GATE_IP_ISP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* GATE_SCLK_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const struct samsung_cmu_info isp_cmu_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .div_clks = isp_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .nr_div_clks = ARRAY_SIZE(isp_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .gate_clks = isp_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .nr_clk_ids = NR_CLKS_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) samsung_cmu_register_one(np, &isp_cmu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { .compatible = "samsung,exynos3250-cmu-isp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .name = "exynos3250-cmu-isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .of_match_table = exynos3250_cmu_isp_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int __init exynos3250_cmu_platform_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return platform_driver_probe(&exynos3250_cmu_isp_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) exynos3250_cmu_isp_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) subsys_initcall(exynos3250_cmu_platform_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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