^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Tomasz Figa <t.figa@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Clock driver for Exynos clock output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EXYNOS_CLKOUT_NR_CLKS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EXYNOS_CLKOUT_PARENTS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EXYNOS_PMU_DEBUG_REG 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_CLKOUT_DISABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_CLKOUT_MUX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS4_CLKOUT_MUX_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EXYNOS5_CLKOUT_MUX_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct exynos_clkout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 pmu_debug_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_hw_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct exynos_clkout *clkout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int exynos_clkout_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void exynos_clkout_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct syscore_ops exynos_clkout_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .suspend = exynos_clkout_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .resume = exynos_clkout_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const char *parent_names[EXYNOS_CLKOUT_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *parents[EXYNOS_CLKOUT_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int parent_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!clkout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spin_lock_init(&clkout->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) parent_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) char name[] = "clkoutXX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) snprintf(name, sizeof(name), "clkout%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) parents[i] = of_clk_get_by_name(node, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (IS_ERR(parents[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) parent_names[i] = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) parent_names[i] = __clk_get_name(parents[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) parent_count = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!parent_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto free_clkout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clkout->reg = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!clkout->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto clks_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clkout->gate.lock = &clkout->slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clkout->mux.mask = mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clkout->mux.lock = &clkout->slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) parent_names, parent_count, &clkout->mux.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &clk_gate_ops, CLK_SET_RATE_PARENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) | CLK_SET_RATE_NO_REPARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (IS_ERR(clkout->data.hws[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto err_clk_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) register_syscore_ops(&exynos_clkout_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) err_clk_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_hw_unregister(clkout->data.hws[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iounmap(clkout->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clks_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!IS_ERR(parents[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_put(parents[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) free_clkout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) kfree(clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_err("%s: failed to register clkout clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * the OF_POPULATED flag on the pmu device tree node, so later the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Exynos PMU platform device can be properly probed with PMU driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void __init exynos4_clkout_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) exynos4_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) exynos4_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) exynos4_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void __init exynos5_clkout_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) exynos5_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) exynos5_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) exynos5_clkout_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) exynos5_clkout_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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