^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Padmavathi Venna <padma.v@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Common Clock Framework support for Audio Subsystem Clock Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/exynos-audss-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static DEFINE_SPINLOCK(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * On Exynos5420 this will be a clock which has to be enabled before any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * access to audss registers. Typically a child of EPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * On other platforms this will be -ENODEV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct clk *epll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASS_CLK_SRC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASS_CLK_DIV 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASS_CLK_GATE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned long reg_save[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { ASS_CLK_SRC, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { ASS_CLK_DIV, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { ASS_CLK_GATE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for (i = 0; i < ARRAY_SIZE(reg_save); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg_save[i][1] = readl(reg_base + reg_save[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) for (i = 0; i < ARRAY_SIZE(reg_save); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(reg_save[i][1], reg_base + reg_save[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct exynos_audss_clk_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int has_adma_clk:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int has_mst_clk:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int enable_epll:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .enable_epll = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .has_mst_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .num_clks = EXYNOS_AUDSS_MAX_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .has_adma_clk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable_epll = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct of_device_id exynos_audss_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .compatible = "samsung,exynos4210-audss-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .data = &exynos4210_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .compatible = "samsung,exynos5250-audss-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .data = &exynos4210_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .compatible = "samsung,exynos5410-audss-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .data = &exynos5410_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .compatible = "samsung,exynos5420-audss-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .data = &exynos5420_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void exynos_audss_clk_teardown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!IS_ERR(clk_data->hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk_hw_unregister_mux(clk_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (; i < EXYNOS_SRP_CLK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!IS_ERR(clk_data->hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clk_hw_unregister_divider(clk_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (; i < clk_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!IS_ERR(clk_data->hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_hw_unregister_gate(clk_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* register exynos_audss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int exynos_audss_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *sclk_pcm_p = "sclk_pcm0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct exynos_audss_clk_drvdata *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk_hw **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) variant = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) epll = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_data = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct_size(clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXYNOS_AUDSS_MAX_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk_data->num = variant->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_table = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pll_ref = devm_clk_get(dev, "pll_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pll_in = devm_clk_get(dev, "pll_in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!IS_ERR(pll_ref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mout_audss_p[0] = __clk_get_name(pll_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!IS_ERR(pll_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mout_audss_p[1] = __clk_get_name(pll_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (variant->enable_epll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) epll = pll_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = clk_prepare_enable(epll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "failed to prepare the epll clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Enable runtime PM here to allow the clock core using runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * for the registered clocks. Additionally, we increase the runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * PM usage count before registering the clocks, to prevent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * clock core from runtime suspending the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mout_audss_p, ARRAY_SIZE(mout_audss_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cdclk = devm_clk_get(dev, "cdclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sclk_audio = devm_clk_get(dev, "sclk_audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!IS_ERR(cdclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mout_i2s_p[1] = __clk_get_name(cdclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!IS_ERR(sclk_audio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mout_i2s_p[2] = __clk_get_name(sclk_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "mout_audss", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "dout_srp", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg_base + ASS_CLK_GATE, 0, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "dout_aud_bus", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg_base + ASS_CLK_GATE, 2, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "dout_i2s", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reg_base + ASS_CLK_GATE, 3, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "sclk_pcm", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg_base + ASS_CLK_GATE, 4, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!IS_ERR(sclk_pcm_in))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sclk_pcm_p = __clk_get_name(sclk_pcm_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sclk_pcm_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg_base + ASS_CLK_GATE, 5, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (variant->has_adma_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "dout_srp", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg_base + ASS_CLK_GATE, 9, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < clk_data->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(clk_table[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "failed to register clock %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = PTR_ERR(clk_table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "failed to add clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) exynos_audss_clk_teardown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!IS_ERR(epll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_disable_unprepare(epll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int exynos_audss_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) exynos_audss_clk_teardown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!IS_ERR(epll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_disable_unprepare(epll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct platform_driver exynos_audss_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "exynos-audss-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .of_match_table = exynos_audss_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .pm = &exynos_audss_clk_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .probe = exynos_audss_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .remove = exynos_audss_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) module_platform_driver(exynos_audss_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_ALIAS("platform:exynos-audss-clk");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags