Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Common Clock Framework support for all PLL's in Samsung platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __SAMSUNG_CLK_CPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __SAMSUNG_CLK_CPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * struct exynos_cpuclk_data: config data to setup cpu clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * @prate: frequency of the primary parent clock (in KHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @div0: value to be programmed in the div_cpu0 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * @div1: value to be programmed in the div_cpu1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * This structure holds the divider configuration data for dividers in the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * clock domain. The parent frequency at which these divider values are valid is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * specified in @prate. The @prate is the frequency of the primary parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * For CPU clock domains that do not have a DIV1 register, the @div1 member
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * value is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct exynos_cpuclk_cfg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned long	prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned long	div0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned long	div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * struct exynos_cpuclk: information about clock supplied to a CPU core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * @hw:	handle between CCF and CPU clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * @alt_parent: alternate parent clock to use when switching the speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  *	of the primary parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * @ctrl_base:	base address of the clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @lock: cpu clock domain register access lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * @cfg: cpu clock rate configuration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @num_cfgs: number of array elements in @cfg array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @clk_nb: clock notifier registered for changes in clock speed of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  *	primary parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * @flags: configuration flags for the CPU clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * This structure holds information required for programming the CPU clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * various clock speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct exynos_cpuclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct clk_hw				hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	const struct clk_hw			*alt_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	void __iomem				*ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	spinlock_t				*lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	const struct exynos_cpuclk_cfg_data	*cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	const unsigned long			num_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct notifier_block			clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	unsigned long				flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* The CPU clock registers have DIV1 configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_CPU_HAS_DIV1		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* When ALT parent is active, debug clocks need safe divider values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_CPU_NEEDS_DEBUG_ALT_DIV	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* The CPU clock registers have Exynos5433-compatible layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_CPU_HAS_E5433_REGS_LAYOUT	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			unsigned int lookup_id, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			const struct clk_hw *parent, const struct clk_hw *alt_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			const struct exynos_cpuclk_cfg_data *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			unsigned long num_cfgs, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* __SAMSUNG_CLK_CPU_H */