^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Wyon Bi <bivvy.bi@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/rk628.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/reset/rk628-rgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/rk628-cgu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK628_PLL(_id, _name, _parent_name, _reg, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PLL(_id, _name, _parent_name, _reg, 13, 12, 10, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG(x) ((x) + 0xc0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CRU_CPLL_CON0 REG(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CRU_CPLL_CON1 REG(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CRU_CPLL_CON2 REG(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CRU_CPLL_CON3 REG(0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRU_CPLL_CON4 REG(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRU_GPLL_CON0 REG(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRU_GPLL_CON1 REG(0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CRU_GPLL_CON2 REG(0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRU_GPLL_CON3 REG(0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRU_GPLL_CON4 REG(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CRU_MODE_CON REG(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CRU_CLKSEL_CON00 REG(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CRU_CLKSEL_CON01 REG(0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CRU_CLKSEL_CON02 REG(0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CRU_CLKSEL_CON03 REG(0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CRU_CLKSEL_CON04 REG(0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CRU_CLKSEL_CON05 REG(0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CRU_CLKSEL_CON06 REG(0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CRU_CLKSEL_CON07 REG(0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CRU_CLKSEL_CON08 REG(0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CRU_CLKSEL_CON09 REG(0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CRU_CLKSEL_CON10 REG(0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CRU_CLKSEL_CON11 REG(0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CRU_CLKSEL_CON12 REG(0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CRU_CLKSEL_CON13 REG(0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CRU_CLKSEL_CON14 REG(0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CRU_CLKSEL_CON15 REG(0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CRU_CLKSEL_CON16 REG(0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CRU_CLKSEL_CON17 REG(0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CRU_CLKSEL_CON18 REG(0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CRU_CLKSEL_CON20 REG(0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CRU_CLKSEL_CON21 REG(0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CRU_GATE_CON00 REG(0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CRU_GATE_CON01 REG(0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CRU_GATE_CON02 REG(0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CRU_GATE_CON03 REG(0x018c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CRU_GATE_CON04 REG(0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CRU_GATE_CON05 REG(0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CRU_SOFTRST_CON00 REG(0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CRU_SOFTRST_CON01 REG(0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CRU_SOFTRST_CON02 REG(0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CRU_SOFTRST_CON04 REG(0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CRU_MAX_REGISTER CRU_SOFTRST_CON04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define reset_to_cru(_rst) container_of(_rst, struct rk628_cru, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct rk628_cru {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct rk628 *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CNAME(x) "rk628_" x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PNAME(x) static const char *const x[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PNAME(mux_cpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_cpll") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PNAME(mux_gpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_gpll") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PNAME(mux_cpll_gpll_mux_p) = { CNAME("clk_cpll_mux"), CNAME("clk_gpll_mux") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PNAME(mux_mclk_i2s_8ch_p) = { CNAME("clk_i2s_8ch_src"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CNAME("clk_i2s_8ch_frac"), CNAME("i2s_mclkin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CNAME("xin_osc0_half") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PNAME(mux_i2s_mclkout_p) = { CNAME("mclk_i2s_8ch"), CNAME("xin_osc0_half") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PNAME(mux_clk_testout_p) = { CNAME("xin_osc0_func"), CNAME("xin_osc0_half"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CNAME("clk_gpll"), CNAME("clk_gpll_mux"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CNAME("clk_cpll"), CNAME("clk_gpll_mux"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CNAME("pclk_logic"), CNAME("sclk_vop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CNAME("mclk_i2s_8ch"), CNAME("i2s_mclkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CNAME("dummy"), CNAME("clk_hdmirx_aud"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CNAME("clk_hdmirx_cec"), CNAME("clk_imodet"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CNAME("clk_txesc"), CNAME("clk_gpio_db0") };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct clk_pll_data rk628_clk_plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK628_PLL(CGU_CLK_CPLL, CNAME("clk_cpll"), CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CRU_CPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK628_PLL(CGU_CLK_GPLL, CNAME("clk_gpll"), CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CRU_GPLL_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct clk_mux_data rk628_clk_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX(CGU_CLK_CPLL_MUX, CNAME("clk_cpll_mux"), mux_cpll_osc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CRU_MODE_CON, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX(CGU_CLK_GPLL_MUX, CNAME("clk_gpll_mux"), mux_gpll_osc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CRU_MODE_CON, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct clk_gate_data rk628_clk_gates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) GATE(CGU_PCLK_GPIO0, CNAME("pclk_gpio0"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CRU_GATE_CON01, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GATE(CGU_PCLK_GPIO1, CNAME("pclk_gpio1"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CRU_GATE_CON01, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GATE(CGU_PCLK_GPIO2, CNAME("pclk_gpio2"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CRU_GATE_CON01, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GATE(CGU_PCLK_GPIO3, CNAME("pclk_gpio3"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CRU_GATE_CON01, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GATE(CGU_PCLK_TXPHY_CON, CNAME("pclk_txphy_con"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CRU_GATE_CON02, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GATE(CGU_PCLK_EFUSE, CNAME("pclk_efuse"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CRU_GATE_CON00, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GATE(0, CNAME("pclk_i2c2apb"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CRU_GATE_CON00, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GATE(0, CNAME("pclk_cru"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CRU_GATE_CON00, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GATE(0, CNAME("pclk_adapter"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CRU_GATE_CON00, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) GATE(0, CNAME("pclk_regfile"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CRU_GATE_CON00, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) GATE(CGU_PCLK_DSI0, CNAME("pclk_dsi0"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CRU_GATE_CON02, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GATE(CGU_PCLK_DSI1, CNAME("pclk_dsi1"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CRU_GATE_CON02, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GATE(CGU_PCLK_CSI, CNAME("pclk_csi"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CRU_GATE_CON02, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GATE(CGU_PCLK_HDMITX, CNAME("pclk_hdmitx"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CRU_GATE_CON02, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GATE(CGU_PCLK_RXPHY, CNAME("pclk_rxphy"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CRU_GATE_CON02, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GATE(CGU_PCLK_HDMIRX, CNAME("pclk_hdmirx"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CRU_GATE_CON02, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GATE(CGU_PCLK_GVIHOST, CNAME("pclk_gvihost"), CNAME("pclk_logic"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CRU_GATE_CON02, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GATE(CGU_CLK_CFG_DPHY0, CNAME("clk_cfg_dphy0"), CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CRU_GATE_CON02, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) GATE(CGU_CLK_CFG_DPHY1, CNAME("clk_cfg_dphy1"), CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CRU_GATE_CON02, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) GATE(CGU_CLK_TXESC, CNAME("clk_txesc"), CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CRU_GATE_CON02, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct clk_composite_data rk628_clk_composites[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) COMPOSITE(CGU_CLK_IMODET, CNAME("clk_imodet"), mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CRU_CLKSEL_CON05, 5, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CRU_CLKSEL_CON05, 0, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CRU_GATE_CON02, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) COMPOSITE(CGU_CLK_HDMIRX_AUD, CNAME("clk_hdmirx_aud"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CRU_CLKSEL_CON05, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CRU_CLKSEL_CON05, 6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CRU_GATE_CON02, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) COMPOSITE_FRAC_NOMUX(CGU_CLK_HDMIRX_CEC, CNAME("clk_hdmirx_cec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CRU_CLKSEL_CON12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CRU_GATE_CON01, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) COMPOSITE_FRAC(CGU_CLK_RX_READ, CNAME("clk_rx_read"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CRU_CLKSEL_CON02, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CRU_CLKSEL_CON14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CRU_GATE_CON00, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) COMPOSITE_FRAC(CGU_SCLK_VOP, CNAME("sclk_vop"), mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CRU_CLKSEL_CON02, 9, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CRU_CLKSEL_CON13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CRU_GATE_CON00, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_SET_RATE_NO_REPARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) COMPOSITE(CGU_PCLK_LOGIC, CNAME("pclk_logic"), mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CRU_CLKSEL_CON00, 7, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CRU_CLKSEL_CON00, 0, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CRU_GATE_CON00, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) COMPOSITE_NOMUX(CGU_CLK_GPIO_DB0, CNAME("clk_gpio_db0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CRU_CLKSEL_CON08, 0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CRU_GATE_CON01, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) COMPOSITE_NOMUX(CGU_CLK_GPIO_DB1, CNAME("clk_gpio_db1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) CRU_CLKSEL_CON09, 0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CRU_GATE_CON01, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) COMPOSITE_NOMUX(CGU_CLK_GPIO_DB2, CNAME("clk_gpio_db2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CRU_CLKSEL_CON10, 0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CRU_GATE_CON01, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) COMPOSITE_NOMUX(CGU_CLK_GPIO_DB3, CNAME("clk_gpio_db3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CNAME("xin_osc0_func"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CRU_CLKSEL_CON11, 0, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CRU_GATE_CON01, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) COMPOSITE(CGU_CLK_I2S_8CH_SRC, CNAME("clk_i2s_8ch_src"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CRU_CLKSEL_CON03, 13, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CRU_CLKSEL_CON03, 8, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CRU_GATE_CON03, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) COMPOSITE_FRAC_NOMUX(CGU_CLK_I2S_8CH_FRAC, CNAME("clk_i2s_8ch_frac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CNAME("clk_i2s_8ch_src"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CRU_CLKSEL_CON04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CRU_GATE_CON03, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) COMPOSITE_NODIV(CGU_MCLK_I2S_8CH, CNAME("mclk_i2s_8ch"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mux_mclk_i2s_8ch_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CRU_CLKSEL_CON03, 14, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CRU_GATE_CON03, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) COMPOSITE_NODIV(CGU_I2S_MCLKOUT, CNAME("i2s_mclkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mux_i2s_mclkout_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CRU_CLKSEL_CON03, 7, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CRU_GATE_CON03, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) COMPOSITE(CGU_BT1120DEC, CNAME("clk_bt1120dec"), mux_cpll_gpll_mux_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CRU_CLKSEL_CON02, 7, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CRU_CLKSEL_CON02, 0, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CRU_GATE_CON00, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) COMPOSITE(CGU_CLK_TESTOUT, CNAME("clk_testout"), mux_clk_testout_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CRU_CLKSEL_CON06, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CRU_CLKSEL_CON06, 8, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CRU_GATE_CON04, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void rk628_clk_add_lookup(struct rk628_cru *cru, struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (cru->clk_data.clks && id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cru->clk_data.clks[id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void rk628_clk_register_muxes(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (i = 0; i < ARRAY_SIZE(rk628_clk_muxes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct clk_mux_data *data = &rk628_clk_muxes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk = devm_clk_regmap_register_mux(cru->dev, data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) data->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cru->regmap, data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) data->shift, data->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(cru->dev, "failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rk628_clk_add_lookup(cru, clk, data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void rk628_clk_register_gates(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < ARRAY_SIZE(rk628_clk_gates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct clk_gate_data *data = &rk628_clk_gates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk = devm_clk_regmap_register_gate(cru->dev, data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) cru->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) data->reg, data->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(cru->dev, "failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rk628_clk_add_lookup(cru, clk, data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void rk628_clk_register_composites(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (i = 0; i < ARRAY_SIZE(rk628_clk_composites); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct clk_composite_data *data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &rk628_clk_composites[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clk = devm_clk_regmap_register_composite(cru->dev, data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) data->parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) data->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) cru->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) data->mux_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) data->mux_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) data->mux_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data->div_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) data->div_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data->div_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) data->div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) data->gate_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data->gate_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(cru->dev, "failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rk628_clk_add_lookup(cru, clk, data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void rk628_clk_register_plls(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for (i = 0; i < ARRAY_SIZE(rk628_clk_plls); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct clk_pll_data *data = &rk628_clk_plls[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk = devm_clk_regmap_register_pll(cru->dev, data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) data->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cru->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) data->pd_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) data->dsmpd_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) data->lock_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(cru->dev, "failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rk628_clk_add_lookup(cru, clk, data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct rk628_rgu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define RSTGEN(_id, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .id = (_id), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .reg = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .bit = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct rk628_rgu_data rk628_rgu_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RSTGEN(RGU_LOGIC, CRU_SOFTRST_CON00, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RSTGEN(RGU_CRU, CRU_SOFTRST_CON00, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RSTGEN(RGU_REGFILE, CRU_SOFTRST_CON00, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RSTGEN(RGU_I2C2APB, CRU_SOFTRST_CON00, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RSTGEN(RGU_EFUSE, CRU_SOFTRST_CON00, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) RSTGEN(RGU_ADAPTER, CRU_SOFTRST_CON00, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RSTGEN(RGU_CLK_RX, CRU_SOFTRST_CON00, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RSTGEN(RGU_BT1120DEC, CRU_SOFTRST_CON00, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) RSTGEN(RGU_VOP, CRU_SOFTRST_CON00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RSTGEN(RGU_GPIO0, CRU_SOFTRST_CON01, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RSTGEN(RGU_GPIO1, CRU_SOFTRST_CON01, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) RSTGEN(RGU_GPIO2, CRU_SOFTRST_CON01, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RSTGEN(RGU_GPIO3, CRU_SOFTRST_CON01, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RSTGEN(RGU_GPIO_DB0, CRU_SOFTRST_CON01, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RSTGEN(RGU_GPIO_DB1, CRU_SOFTRST_CON01, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) RSTGEN(RGU_GPIO_DB2, CRU_SOFTRST_CON01, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RSTGEN(RGU_GPIO_DB3, CRU_SOFTRST_CON01, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RSTGEN(RGU_RXPHY, CRU_SOFTRST_CON02, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RSTGEN(RGU_HDMIRX, CRU_SOFTRST_CON02, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RSTGEN(RGU_TXPHY_CON, CRU_SOFTRST_CON02, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RSTGEN(RGU_HDMITX, CRU_SOFTRST_CON02, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RSTGEN(RGU_GVIHOST, CRU_SOFTRST_CON02, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) RSTGEN(RGU_DSI0, CRU_SOFTRST_CON02, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) RSTGEN(RGU_DSI1, CRU_SOFTRST_CON02, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RSTGEN(RGU_CSI, CRU_SOFTRST_CON02, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RSTGEN(RGU_TXDATA, CRU_SOFTRST_CON02, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) RSTGEN(RGU_DECODER, CRU_SOFTRST_CON02, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RSTGEN(RGU_ENCODER, CRU_SOFTRST_CON02, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RSTGEN(RGU_HDMIRX_PON, CRU_SOFTRST_CON02, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RSTGEN(RGU_TXBYTEHS, CRU_SOFTRST_CON02, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RSTGEN(RGU_TXESC, CRU_SOFTRST_CON02, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int rk628_rgu_update(struct rk628_cru *cru, unsigned long id, int assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct rk628_rgu_data *data = &rk628_rgu_data[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return regmap_write(cru->regmap, data->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BIT(data->bit + 16) | (assert << data->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int rk628_rgu_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct rk628_cru *cru = reset_to_cru(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return rk628_rgu_update(cru, id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int rk628_rgu_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct rk628_cru *cru = reset_to_cru(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return rk628_rgu_update(cru, id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static struct reset_control_ops rk628_rgu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .assert = rk628_rgu_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .deassert = rk628_rgu_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int rk628_reset_controller_register(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct device *dev = cru->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cru->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cru->rcdev.nr_resets = ARRAY_SIZE(rk628_rgu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cru->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cru->rcdev.ops = &rk628_rgu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return devm_reset_controller_register(dev, &cru->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct regmap_range rk628_cru_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct regmap_access_table rk628_cru_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .yes_ranges = rk628_cru_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct regmap_config rk628_cru_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = "cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .max_register = CRU_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .rd_table = &rk628_cru_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void rk628_cru_init(struct rk628_cru *cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 mcu_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regmap_read(cru->parent->grf, GRF_SYSTEM_STATUS0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mcu_mode = (val & I2C_ONLY_FLAG) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (mcu_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* clock switch and first set gpll almost 99MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff701d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* set clk_gpll_mux from gpll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* set pclk_logic from clk_gpll_mux and set pclk div 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0083);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* set cpll almost 400MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff3063);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* set clk_cpll_mux from clk_cpll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* set pclk use cpll, now div is 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* set pclk use cpll, now div is 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* gpll 983.04MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff1028);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* set pclk use gpll, nuw div is 0xb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff008b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* set cpll 1188MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff1063);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* set pclk use cpll, and set pclk 99MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int rk628_cru_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct rk628_cru *cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct clk **clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cru = devm_kzalloc(dev, sizeof(*cru), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cru->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cru->parent = rk628;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) platform_set_drvdata(pdev, cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cru->regmap = devm_regmap_init_i2c(rk628->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &rk628_cru_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (IS_ERR(cru->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = PTR_ERR(cru->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(dev, "failed to allocate register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rk628_cru_init(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) clk_table = devm_kcalloc(dev, CGU_NR_CLKS, sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!clk_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < CGU_NR_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clk_table[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cru->clk_data.clks = clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) cru->clk_data.clk_num = CGU_NR_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rk628_clk_register_plls(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rk628_clk_register_muxes(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rk628_clk_register_gates(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rk628_clk_register_composites(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rk628_reset_controller_register(cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_prepare_enable(clk_table[CGU_PCLK_LOGIC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) &cru->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int rk628_cru_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct of_device_id rk628_cru_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { .compatible = "rockchip,rk628-cru", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_DEVICE_TABLE(of, rk628_cru_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct platform_driver rk628_cru_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "rk628-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .of_match_table = of_match_ptr(rk628_cru_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .probe = rk628_cru_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .remove = rk628_cru_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) module_platform_driver(rk628_cru_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_DESCRIPTION("Rockchip RK628 CRU driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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