^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef __CLK_REGMAP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __CLK_REGMAP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 pd_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 dsmpd_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 lock_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLL(_id, _name, _parent_name, _reg, _pd_shift, _dsmpd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) _lock_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .pd_shift = _pd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .dsmpd_shift = _dsmpd_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .lock_shift = _lock_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RK618_PLL(_id, _name, _parent_name, _reg, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PLL(_id, _name, _parent_name, _reg, 10, 9, 15, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_mux_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const char *const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MUX(_id, _name, _parent_names, _reg, _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .parent_names = _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .num_parents = ARRAY_SIZE(_parent_names), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GATE(_id, _name, _parent_name, _reg, _shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_divider_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DIV(_id, _name, _parent_name, _reg, _shift, _width, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .parent_name = _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk_composite_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 mux_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define COMPOSITE(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) _div_reg, _div_shift, _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) _gate_reg, _gate_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .parent_names = _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_parents = ARRAY_SIZE(_parent_names), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .mux_reg = _mux_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mux_shift = _mux_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .mux_width = _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .div_reg = _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .div_shift = _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .div_width = _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .div_flags = CLK_DIVIDER_HIWORD_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define COMPOSITE_NOMUX(_id, _name, _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) _div_reg, _div_shift, _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) _gate_reg, _gate_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parent_names = (const char *[]){ _parent_name }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .div_reg = _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .div_shift = _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .div_width = _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .div_flags = CLK_DIVIDER_HIWORD_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define COMPOSITE_NODIV(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) _gate_reg, _gate_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) COMPOSITE(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0, 0, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) _gate_reg, _gate_shift, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define COMPOSITE_FRAC(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) _gate_reg, _gate_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .parent_names = _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_parents = ARRAY_SIZE(_parent_names), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mux_reg = _mux_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mux_shift = _mux_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .mux_width = _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .div_reg = _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define COMPOSITE_FRAC_NOMUX(_id, _name, _parent_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) _gate_reg, _gate_shift, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .parent_names = (const char *[]){ _parent_name }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .div_reg = _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define COMPOSITE_FRAC_NOGATE(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) COMPOSITE_FRAC(_id, _name, _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) _mux_reg, _mux_shift, _mux_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) _div_reg, 0, 0, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_regmap_fractional_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 mshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 mwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 mmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 nshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 nwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 nmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct clk_regmap_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk_regmap_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct clk_regmap_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) extern const struct clk_ops clk_regmap_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) extern const struct clk_ops clk_regmap_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) extern const struct clk_ops clk_regmap_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) extern const struct clk_ops clk_regmap_fractional_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) devm_clk_regmap_register_pll(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct regmap *regmap, u32 reg, u8 pd_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 dsmpd_shift, u8 lock_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) devm_clk_regmap_register_mux(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct regmap *regmap, u32 reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) devm_clk_regmap_register_divider(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const char *parent_name, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) devm_clk_regmap_register_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct regmap *regmap, u32 reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) devm_clk_regmap_register_fractional_divider(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 reg, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) devm_clk_regmap_register_composite(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 num_parents, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 mux_reg, u8 mux_shift, u8 mux_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 div_reg, u8 div_shift, u8 div_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 gate_reg, u8 gate_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags