Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Base on code in drivers/clk/clk-mux.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * See clk-mux.c for further copyright information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define to_clk_regmap_mux(_hw)	container_of(_hw, struct clk_regmap_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static u8 clk_regmap_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	regmap_read(mux->regmap, mux->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	index = val >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	index &= mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return regmap_write(mux->regmap, mux->reg, (index << mux->shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			    (mux->mask << (mux->shift + 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct clk_ops clk_regmap_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.set_parent = clk_regmap_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.get_parent = clk_regmap_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) devm_clk_regmap_register_mux(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			     const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			     struct regmap *regmap, u32 reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			     unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct clk_regmap_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	init.ops = &clk_regmap_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	mux->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	mux->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	mux->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	mux->mask = BIT(width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	return devm_clk_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) EXPORT_SYMBOL_GPL(devm_clk_regmap_register_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_LICENSE("GPL");