^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Base on code in drivers/clk/clk-gate.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * See clk-gate.c for further copyright information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define to_clk_regmap_gate(_hw) container_of(_hw, struct clk_regmap_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int clk_regmap_gate_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_regmap_gate *gate = to_clk_regmap_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return regmap_write(gate->regmap, gate->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0 | BIT(gate->shift + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void clk_regmap_gate_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_regmap_gate *gate = to_clk_regmap_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_write(gate->regmap, gate->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) BIT(gate->shift) | BIT(gate->shift + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int clk_regmap_gate_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk_regmap_gate *gate = to_clk_regmap_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_read(gate->regmap, gate->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return !(val & BIT(gate->shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct clk_ops clk_regmap_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .prepare = clk_regmap_gate_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .unprepare = clk_regmap_gate_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .is_prepared = clk_regmap_gate_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) devm_clk_regmap_register_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct regmap *regmap, u32 reg, u8 shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_regmap_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) init.ops = &clk_regmap_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) gate->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) gate->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) gate->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return devm_clk_register(dev, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EXPORT_SYMBOL_GPL(devm_clk_regmap_register_gate);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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