Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Base on code in drivers/clk/clk-composite.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * See clk-composite.c for further copyright information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "clk-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct clk_regmap_composite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct clk_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct clk_hw *mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct clk_hw *rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct clk_hw *gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	const struct clk_ops *mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	const struct clk_ops *rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	const struct clk_ops *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define to_clk_regmap_composite(_hw)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		container_of(_hw, struct clk_regmap_composite, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static u8 clk_regmap_composite_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return mux_ops->get_parent(mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int clk_regmap_composite_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return mux_ops->set_parent(mux_hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static unsigned long clk_regmap_composite_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 						      unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return rate_ops->recalc_rate(rate_hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int clk_regmap_composite_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					       struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	long tmp_rate, best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned long rate_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long best_rate_diff = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (rate_hw && rate_ops && rate_ops->determine_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return rate_ops->determine_rate(rate_hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		   mux_hw && mux_ops && mux_ops->set_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		req->best_parent_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			parent = clk_hw_get_parent(mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			req->best_parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			rate = rate_ops->round_rate(rate_hw, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 						    &req->best_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			if (rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			req->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			parent = clk_hw_get_parent_by_index(mux_hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 							&parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			if (tmp_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			rate_diff = abs(req->rate - tmp_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			if (!rate_diff || !req->best_parent_hw ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			    best_rate_diff > rate_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				req->best_parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				best_rate_diff = rate_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			if (!rate_diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return mux_ops->determine_rate(mux_hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static long clk_regmap_composite_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					    unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 					    unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return rate_ops->round_rate(rate_hw, rate, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int clk_regmap_composite_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					 unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 					 unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return rate_ops->set_rate(rate_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int clk_regmap_composite_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return gate_ops->is_prepared(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int clk_regmap_composite_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return gate_ops->prepare(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void clk_regmap_composite_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct clk_regmap_composite *composite = to_clk_regmap_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	gate_ops->unprepare(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) devm_clk_regmap_register_composite(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				   const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				   u8 num_parents, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				   u32 mux_reg, u8 mux_shift, u8 mux_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				   u32 div_reg, u8 div_shift, u8 div_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				   u8 div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				   u32 gate_reg, u8 gate_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				   unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct clk_regmap_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct clk_regmap_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct clk_regmap_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct clk_regmap_fractional_divider *fd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	const struct clk_ops *mux_ops = NULL, *div_ops = NULL, *gate_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	const struct clk_ops *fd_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct clk_hw *fd_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct clk_regmap_composite *composite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct clk_ops *clk_composite_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (num_parents > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		mux->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		mux->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		mux->reg = mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		mux->shift = mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		mux->mask = BIT(mux_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		mux_ops = &clk_regmap_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (gate_reg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		gate->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		gate->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		gate->reg = gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		gate->shift = gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		gate_ops = &clk_regmap_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (div_reg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		if (div_flags & CLK_DIVIDER_HIWORD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			div->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			div->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			div->reg = div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			div->shift = div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			div->width = div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			div_ops = &clk_regmap_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			div_hw = &div->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			fd = devm_kzalloc(dev, sizeof(*fd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			if (!fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			fd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			fd->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			fd->reg = div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			fd->mshift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			fd->mwidth = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			fd->mmask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			fd->nshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			fd->nwidth = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			fd->nmask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			fd_ops = &clk_regmap_fractional_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			fd_hw = &fd->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	composite = devm_kzalloc(dev, sizeof(*composite), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!composite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	clk_composite_ops = &composite->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (mux_hw && mux_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (!mux_ops->get_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		composite->mux_hw = mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		composite->mux_ops = mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		clk_composite_ops->get_parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			clk_regmap_composite_get_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		if (mux_ops->set_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			clk_composite_ops->set_parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				clk_regmap_composite_set_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (mux_ops->determine_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			clk_composite_ops->determine_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				clk_regmap_composite_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (div_hw && div_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (!div_ops->recalc_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		clk_composite_ops->recalc_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			clk_regmap_composite_recalc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		if (div_ops->determine_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			clk_composite_ops->determine_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				clk_regmap_composite_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		else if (div_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			clk_composite_ops->round_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				clk_regmap_composite_round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		/* .set_rate requires either .round_rate or .determine_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (div_ops->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			if (div_ops->determine_rate || div_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				clk_composite_ops->set_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					clk_regmap_composite_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				WARN(1, "missing round_rate op\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		composite->rate_hw = div_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		composite->rate_ops = div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (fd_hw && fd_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		if (!fd_ops->recalc_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		clk_composite_ops->recalc_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			clk_regmap_composite_recalc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		if (fd_ops->determine_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			clk_composite_ops->determine_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				clk_regmap_composite_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		else if (fd_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			clk_composite_ops->round_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				clk_regmap_composite_round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		/* .set_rate requires either .round_rate or .determine_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (fd_ops->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			if (fd_ops->determine_rate || fd_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 				clk_composite_ops->set_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 					clk_regmap_composite_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 				WARN(1, "missing round_rate op\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		composite->rate_hw = fd_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		composite->rate_ops = fd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (gate_hw && gate_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		if (!gate_ops->is_prepared || !gate_ops->prepare ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		    !gate_ops->unprepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		composite->gate_hw = gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		composite->gate_ops = gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		clk_composite_ops->is_prepared =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			clk_regmap_composite_is_prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		clk_composite_ops->prepare = clk_regmap_composite_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		clk_composite_ops->unprepare = clk_regmap_composite_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	init.ops = clk_composite_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	composite->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	composite->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	clk = devm_clk_register(dev, &composite->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (composite->mux_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		composite->mux_hw->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (composite->rate_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		composite->rate_hw->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (composite->gate_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		composite->gate_hw->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) EXPORT_SYMBOL_GPL(devm_clk_regmap_register_composite);