^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * samsung/clk.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef CLK_ROCKCHIP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_ROCKCHIP_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BOOST_PLL_H_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BOOST_CLK_CON 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BOOST_BOOST_CON 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BOOST_SWITCH_CNT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BOOST_HIGH_PERF_CNT0 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BOOST_HIGH_PERF_CNT1 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BOOST_STATIS_THRESHOLD 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BOOST_SHORT_SWITCH_CNT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BOOST_SWITCH_THRESHOLD 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BOOST_FSM_STATUS 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BOOST_PLL_CON_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BOOST_CORE_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BOOST_CORE_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BOOST_BACKUP_PLL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BOOST_BACKUP_PLL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BOOST_BACKUP_PLL_USAGE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BOOST_BACKUP_PLL_USAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BOOST_BACKUP_PLL_USAGE_BORROW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BOOST_BACKUP_PLL_USAGE_TARGET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BOOST_ENABLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BOOST_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BOOST_RECOVERY_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BOOST_RECOVERY_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BOOST_SW_CTRL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BOOST_SW_CTRL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BOOST_LOW_FREQ_EN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BOOST_LOW_FREQ_EN_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BOOST_STATIS_ENABLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BOOST_STATIS_ENABLE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BOOST_BUSY_STATE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PX30_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PX30_GLB_SRST_FST 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PX30_GLB_SRST_SND 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PX30_MODE_CON 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PX30_MISC_CON 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PX30_SDMMC_CON0 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PX30_SDMMC_CON1 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PX30_SDIO_CON0 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PX30_SDIO_CON1 0x38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PX30_EMMC_CON0 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PX30_EMMC_CON1 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PX30_PMU_MODE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RV1106_TOPCRU_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RV1106_PERICRU_BASE 0x12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RV1106_VICRU_BASE 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RV1106_NPUCRU_BASE 0x16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RV1106_CORECRU_BASE 0x18000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RV1106_VEPUCRU_BASE 0x1A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RV1106_VOCRU_BASE 0x1C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RV1106_DDRCRU_BASE 0x1E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RV1106_SUBDDRCRU_BASE 0x1F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RV1106_VI_GRF_BASE 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RV1106_VO_GRF_BASE 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RV1106_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RV1106_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RV1106_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RV1106_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RV1106_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RV1106_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RV1106_GLB_SRST_FST (0xc08 + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RV1106_GLB_SRST_SND (0xc0c + RV1106_TOPCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RV1106_SDIO_CON0 (0x1c + RV1106_VO_GRF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RV1106_SDIO_CON1 (0x20 + RV1106_VO_GRF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RV1106_SDMMC_CON0 (0x4 + RV1106_VI_GRF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RV1106_SDMMC_CON1 (0x8 + RV1106_VI_GRF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RV1106_EMMC_CON0 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RV1106_EMMC_CON1 (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RV1106_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RV1106_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RV1106_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RV1106_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RV1106_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RV1106_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RV1106_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RV1106_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RV1106_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RV1106_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RV1106_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RV1106_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RV1106_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RV1106_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RV1106_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RV1106_VOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RV1106_VOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RV1106_VOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RV1106_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RV1106_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RV1106_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RV1106_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RV1106_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RV1106_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RV1108_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RV1108_GLB_SRST_FST 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RV1108_GLB_SRST_SND 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RV1108_MISC_CON 0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RV1108_SDMMC_CON0 0x1d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RV1108_SDMMC_CON1 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RV1108_SDIO_CON0 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RV1108_SDIO_CON1 0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RV1108_EMMC_CON0 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RV1108_EMMC_CON1 0x1ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RV1126_PMU_MODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RV1126_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RV1126_MODE_CON 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RV1126_GLB_SRST_FST 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RV1126_GLB_SRST_SND 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RV1126_SDMMC_CON0 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RV1126_SDMMC_CON1 0x444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RV1126_SDIO_CON0 0x448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RV1126_SDIO_CON1 0x44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RV1126_EMMC_CON0 0x450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RV1126_EMMC_CON1 0x454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * register positions shared by RK1808 RK2928, RK3036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * RK3066, RK3188 and RK3228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RK1808_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RK1808_MODE_CON 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RK1808_MISC_CON 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RK1808_MISC1_CON 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RK1808_GLB_SRST_FST 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RK1808_GLB_SRST_SND 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RK1808_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RK1808_CLKGATE_CON(x) ((x) * 0x4 + 0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RK1808_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RK1808_SDMMC_CON0 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RK1808_SDMMC_CON1 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RK1808_SDIO_CON0 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RK1808_SDIO_CON1 0x38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RK1808_EMMC_CON0 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RK1808_EMMC_CON1 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RK1808_PMU_MODE_CON 0x4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RK1808_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x4040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RK1808_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x4080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RK2928_PLL_CON(x) ((x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RK2928_MODE_CON 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RK2928_GLB_SRST_FST 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RK2928_GLB_SRST_SND 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RK2928_MISC_CON 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RK3036_SDMMC_CON0 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RK3036_SDMMC_CON1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RK3036_SDIO_CON0 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RK3036_SDIO_CON1 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RK3036_EMMC_CON0 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RK3036_EMMC_CON1 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RK3228_GLB_SRST_FST 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RK3228_GLB_SRST_SND 0x1f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RK3228_SDMMC_CON0 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RK3228_SDMMC_CON1 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RK3228_SDIO_CON0 0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RK3228_SDIO_CON1 0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RK3228_EMMC_CON0 0x1d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RK3228_EMMC_CON1 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RK3288_MODE_CON 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RK3288_GLB_SRST_FST 0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RK3288_GLB_SRST_SND 0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RK3288_MISC_CON 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RK3288_SDMMC_CON0 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RK3288_SDMMC_CON1 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RK3288_SDIO0_CON0 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RK3288_SDIO0_CON1 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RK3288_SDIO1_CON0 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RK3288_SDIO1_CON1 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define RK3288_EMMC_CON0 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define RK3288_EMMC_CON1 0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define RK3308_GLB_SRST_FST 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RK3308_MODE_CON 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RK3308_SDMMC_CON0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RK3308_SDMMC_CON1 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RK3308_SDIO_CON0 0x488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RK3308_SDIO_CON1 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RK3308_EMMC_CON0 0x490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RK3308_EMMC_CON1 0x494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define RK3328_GLB_SRST_FST 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define RK3328_GLB_SRST_SND 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define RK3328_MODE_CON 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RK3328_MISC_CON 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define RK3328_SDMMC_CON0 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RK3328_SDMMC_CON1 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define RK3328_SDIO_CON0 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RK3328_SDIO_CON1 0x38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define RK3328_EMMC_CON0 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RK3328_EMMC_CON1 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RK3328_SDMMC_EXT_CON0 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RK3328_SDMMC_EXT_CON1 0x39C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define RK3368_GLB_SRST_FST 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RK3368_GLB_SRST_SND 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RK3368_MISC_CON 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RK3368_SDMMC_CON0 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RK3368_SDMMC_CON1 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RK3368_SDIO0_CON0 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define RK3368_SDIO0_CON1 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RK3368_SDIO1_CON0 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RK3368_SDIO1_CON1 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define RK3368_EMMC_CON0 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RK3368_EMMC_CON1 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define RK3399_GLB_SRST_FST 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RK3399_GLB_SRST_SND 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RK3399_GLB_CNT_TH 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define RK3399_MISC_CON 0x50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define RK3399_RST_CON 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define RK3399_RST_ST 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RK3399_SDMMC_CON0 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define RK3399_SDMMC_CON1 0x584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define RK3399_SDIO_CON0 0x588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define RK3399_SDIO_CON1 0x58c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define RK3568_MODE_CON0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define RK3568_MISC_CON0 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RK3568_MISC_CON1 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RK3568_MISC_CON2 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RK3568_GLB_CNT_TH 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RK3568_GLB_SRST_FST 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RK3568_GLB_SRST_SND 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RK3568_GLB_RST_CON 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RK3568_GLB_RST_ST 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RK3568_SDMMC0_CON0 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RK3568_SDMMC0_CON1 0x584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RK3568_SDMMC1_CON0 0x588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RK3568_SDMMC1_CON1 0x58c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define RK3568_SDMMC2_CON0 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RK3568_SDMMC2_CON1 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RK3568_EMMC_CON0 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RK3568_EMMC_CON1 0x59c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define RK3568_PMU_MODE_CON0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define RK3588_PHP_CRU_BASE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define RK3588_PMU_CRU_BASE 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define RK3588_BIGCORE0_CRU_BASE 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define RK3588_BIGCORE1_CRU_BASE 0x52000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RK3588_DSU_CRU_BASE 0x58000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define RK3588_PLL_CON(x) RK2928_PLL_CON(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define RK3588_MODE_CON0 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define RK3588_GLB_CNT_TH 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define RK3588_GLB_SRST_FST 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define RK3588_GLB_SRST_SND 0xc0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RK3588_GLB_RST_CON 0xc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RK3588_GLB_RST_ST 0xc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define RK3588_SDIO_CON0 0xC24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define RK3588_SDIO_CON1 0xC28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RK3588_SDMMC_CON0 0xC30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define RK3588_SDMMC_CON1 0xC34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) enum rockchip_pll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pll_rk3036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pll_rk3066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pll_rk3328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pll_rk3399,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pll_rk3588,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pll_rk3588_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) _postdiv2, _dsmpd, _frac) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .rate = _rate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .fbdiv = _fbdiv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .postdiv1 = _postdiv1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .refdiv = _refdiv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .postdiv2 = _postdiv2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .dsmpd = _dsmpd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .frac = _frac, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .rate = _rate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .nr = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .nf = _nf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .no = _no, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .rate = _rate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .nr = _nr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .nf = _nf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .no = _no, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .nb = _nb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .rate = _rate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .p = _p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .m = _m, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .s = _s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .k = _k, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * struct rockchip_clk_provider - information about clock provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @reg_base: virtual address for the register base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @clk_data: holds clock related data like clk* and number of clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @cru_node: device-node of the clock-provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @grf: regmap of the general-register-files syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @lock: maintains exclusion between callbacks for a given clock-provider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct rockchip_clk_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct device_node *cru_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct regmap *pmugrf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct rockchip_pll_rate_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* for RK3066 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* for RK3036/RK3399 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int postdiv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int postdiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int dsmpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* for RK3588 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned int s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * struct rockchip_pll_clock - information about pll clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @id: platform specific id of the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @name: name of this pll clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @parent_names: name of the parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @num_parents: number of parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @flags: optional flags for basic clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @con_offset: offset of the register for configuring the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @mode_offset: offset of the register for configuring the PLL-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @mode_shift: offset inside the mode-register for the mode of this pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @lock_shift: offset inside the lock register for the lock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * @type: Type of PLL to be registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @pll_flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * @rate_table: Table of usable pll rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * rate_table parameters and ajust them if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct rockchip_pll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const char *const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int con_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int mode_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int lock_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) enum rockchip_pll_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 pll_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct rockchip_pll_rate_table *rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) _lshift, _pflags, _rtable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .parent_names = _pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .num_parents = ARRAY_SIZE(_pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .flags = CLK_GET_RATE_NOCACHE | _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .con_offset = _con, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mode_offset = _mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mode_shift = _mshift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .lock_shift = _lshift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .pll_flags = _pflags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .rate_table = _rtable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum rockchip_pll_type pll_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const char *name, const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 num_parents, int con_offset, int grf_lock_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int lock_shift, int mode_offset, int mode_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct rockchip_pll_rate_table *rate_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned long flags, u8 clk_pll_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void rockchip_boost_init(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) void rockchip_boost_enable_recovery_sw_low(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) void rockchip_boost_disable_recovery_sw(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void rockchip_boost_add_core_div(struct clk_hw *hw, unsigned long prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct rockchip_cpuclk_clksel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define ROCKCHIP_CPUCLK_MAX_CORES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct rockchip_cpuclk_rate_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @core_reg[]: register offset of the cores setting register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @div_core_shift[]: cores divider offset used to divide the pll value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @div_core_mask[]: cores divider mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @num_cores: number of cpu cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @mux_core_reg: register offset of the cores select parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @mux_core_alt: mux value to select alternate parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * @mux_core_main: mux value to select main parent of core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * @mux_core_shift: offset of the core multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * @mux_core_mask: core multiplexer mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct rockchip_cpuclk_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int num_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int mux_core_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u8 mux_core_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 mux_core_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 mux_core_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 mux_core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const char *pll_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct clk *rockchip_clk_register_cpuclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct clk *parent, struct clk *alt_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct rockchip_cpuclk_reg_data *reg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const struct rockchip_cpuclk_rate_table *rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int nrates, void __iomem *reg_base, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct clk *rockchip_clk_register_mmc(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) const char *const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) void __iomem *reg, int shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * DDRCLK flags, including method of setting the rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define ROCKCHIP_DDRCLK_SIP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define ROCKCHIP_DDRCLK_SCPI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ROCKCHIP_DDRCLK_SIP_V2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #ifdef CONFIG_ROCKCHIP_DDRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void rockchip_set_ddrclk_params(void __iomem *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 num_parents, int mux_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int mux_shift, int mux_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int div_shift, int div_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int ddr_flags, void __iomem *reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static inline void rockchip_set_ddrclk_params(void __iomem *params) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static inline void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void)) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u8 num_parents, int mux_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int mux_shift, int mux_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int div_shift, int div_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int ddr_flags, void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct clk *rockchip_clk_register_inverter(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const char *const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) void __iomem *reg, int shift, int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct clk *rockchip_clk_register_muxgrf(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) const char *const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int flags, struct regmap *grf, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int shift, int width, int mux_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define PNAME(x) static const char *const x[] __initconst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) enum rockchip_clk_branch_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) branch_composite,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) branch_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) branch_muxgrf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) branch_muxpmugrf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) branch_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) branch_fraction_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) branch_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) branch_mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) branch_inverter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) branch_factor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) branch_ddrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) branch_half_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct rockchip_clk_branch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) enum rockchip_clk_branch_type branch_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const char *const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int muxdiv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u8 mux_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int div_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int gate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct rockchip_clk_branch *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) df, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mt, ds, dw, df, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .mux_table = mt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mf, do, ds, dw, df, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .div_offset = do, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) df, dt, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .div_table = dt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ds, dw, df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mw, mf, ds, dw, df, dt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .branch_type = branch_composite, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .div_table = dt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .branch_type = branch_fraction_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .div_shift = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .div_width = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .branch_type = branch_fraction_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .div_shift = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .div_width = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .child = ch, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .branch_type = branch_fraction_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .div_shift = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .div_width = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .child = ch, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ds, dw, df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .branch_type = branch_ddrclk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define MUX(_id, cname, pnames, f, o, s, w, mf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .branch_type = branch_mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .mux_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .mux_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .branch_type = branch_mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .mux_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .mux_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .mux_table = mt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .branch_type = branch_muxgrf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .mux_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .mux_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .branch_type = branch_muxpmugrf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .mux_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .mux_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define DIV(_id, cname, pname, f, o, s, w, df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .branch_type = branch_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .div_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .div_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .branch_type = branch_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .div_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .div_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .div_table = dt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define GATE(_id, cname, pname, f, o, b, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .branch_type = branch_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .gate_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .gate_shift = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define MMC(_id, cname, pname, offset, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .branch_type = branch_mmc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .muxdiv_offset = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .div_shift = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define INVERTER(_id, cname, pname, io, is, if) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .branch_type = branch_inverter, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .muxdiv_offset = io, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .div_shift = is, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .div_flags = if, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define FACTOR(_id, cname, pname, f, fm, fd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .branch_type = branch_factor, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .div_shift = fm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .div_width = fd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .branch_type = branch_factor, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .div_shift = fm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .div_width = fd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .gate_shift = gb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) df, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .branch_type = branch_half_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define COMPOSITE_HALFDIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, mf, do,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ds, dw, df, go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .branch_type = branch_half_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .div_offset = do, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ds, dw, df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .branch_type = branch_half_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .parent_names = pnames, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .num_parents = ARRAY_SIZE(pnames), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .mux_shift = ms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .mux_width = mw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .mux_flags = mf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) go, gs, gf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .branch_type = branch_half_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .muxdiv_offset = mo, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .div_shift = ds, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .div_width = dw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .gate_offset = go, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .gate_shift = gs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .gate_flags = gf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .branch_type = branch_half_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .name = cname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .parent_names = (const char *[]){ pname }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .flags = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .muxdiv_offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .div_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .div_width = w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .div_flags = df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .gate_offset = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* SGRF clocks are only accessible from secure mode, so not controllable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SGRF_GATE(_id, cname, pname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) FACTOR(_id, cname, pname, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) void __iomem *base, unsigned long nr_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) void rockchip_clk_of_add_provider(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct rockchip_clk_provider *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct clk *clk, unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct rockchip_clk_branch *list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) unsigned int nr_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct rockchip_pll_clock *pll_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) unsigned int nr_pll, int grf_lock_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned int lookup_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct clk *parent, struct clk *alt_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) const struct rockchip_cpuclk_reg_data *reg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) const struct rockchip_cpuclk_rate_table *rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int nrates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) unsigned int reg, void (*cb)(void));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct clk *rockchip_clk_register_halfdiv(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) const char *const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u8 num_parents, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int muxdiv_offset, u8 mux_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u8 mux_width, u8 mux_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) int div_offset, u8 div_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) u8 div_width, u8 div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) int gate_offset, u8 gate_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u8 gate_flags, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #ifdef CONFIG_RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) void rockchip_register_softrst(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) unsigned int num_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) void __iomem *base, u8 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static inline void rockchip_register_softrst(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) unsigned int num_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) void __iomem *base, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) extern void (*rk_dump_cru)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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