^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Finley Xiao <finley.xiao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/rv1126-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RV1126_GMAC_CON 0x460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RV1126_GRF_IOFUNC_CON1 0x10264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RV1126_GRF_SOC_STATUS0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RV1126_PMUGRF_SOC_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RV1126_FRAC_MAX_PRATE 1200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum rv1126_pmu_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum rv1126_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) apll, dpll, cpll, hpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_ROCKCHIP_LOW_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RV1126_DIV_ACLK_CORE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RV1126_DIV_ACLK_CORE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RV1126_DIV_PCLK_DBG_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RV1126_DIV_PCLK_DBG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .reg = RV1126_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RV1126_DIV_ACLK_CORE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RV1126_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RV1126_CPUCLK_RATE(1608000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RV1126_CPUCLK_RATE(1584000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RV1126_CPUCLK_RATE(1560000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RV1126_CPUCLK_RATE(1536000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RV1126_CPUCLK_RATE(1512000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RV1126_CPUCLK_RATE(1488000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RV1126_CPUCLK_RATE(1464000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RV1126_CPUCLK_RATE(1440000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RV1126_CPUCLK_RATE(1416000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RV1126_CPUCLK_RATE(1392000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RV1126_CPUCLK_RATE(1368000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RV1126_CPUCLK_RATE(1344000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RV1126_CPUCLK_RATE(1320000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) RV1126_CPUCLK_RATE(1296000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RV1126_CPUCLK_RATE(1272000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) RV1126_CPUCLK_RATE(1248000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RV1126_CPUCLK_RATE(1224000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RV1126_CPUCLK_RATE(1200000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RV1126_CPUCLK_RATE(1104000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RV1126_CPUCLK_RATE(1008000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RV1126_CPUCLK_RATE(912000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) RV1126_CPUCLK_RATE(816000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RV1126_CPUCLK_RATE(696000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RV1126_CPUCLK_RATE(600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RV1126_CPUCLK_RATE(408000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) RV1126_CPUCLK_RATE(312000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) RV1126_CPUCLK_RATE(216000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) RV1126_CPUCLK_RATE(96000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .core_reg[0] = RV1126_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mux_core_alt = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .mux_core_main = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_pll_p) = { "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PNAME(mux_clk_32k_ioe_p) = { "xin32k", "clk_rtc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "dummy_cpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "dummy_cpll", "dummy_dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "dummy_cpll", "usb480m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PNAME(mux_cpll_gpll_p) = { "dummy_cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "dummy_cpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PNAME(mux_cpll_hpll_gpll_p) = { "dummy_cpll", "dummy_hpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PNAME(mux_cpll_gpll_hpll_p) = { "dummy_cpll", "gpll", "dummy_hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "dummy_cpll", "dummy_hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "dummy_cpll", "dummy_apll", "dummy_hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CLK_IS_CRITICAL, RV1126_PMU_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK_IGNORE_UNUSED, RV1126_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CLK_IGNORE_UNUSED, RV1126_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RV1126_MODE_CON, 2, 1, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CLK_IS_CRITICAL, RV1126_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CLK_IS_CRITICAL, RV1126_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0, RV1126_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0, RV1126_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct rockchip_clk_branch rv1126_cif_out2io_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX(CLK_CIF_OUT_MUX, "clk_cif_out2io_mux", mux_cif_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RV1126_CLKSEL_CON(50), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct rockchip_clk_branch rv1126_mipicsi_out2io_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MUX(CLK_MIPICSI_OUT_MUX, "clk_mipicsi_out2io_mux", mux_mipicsi_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RV1126_CLKSEL_CON(73), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* PD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RV1126_PMU_CLKSEL_CON(13), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &rv1126_rtc32k_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MUXPMUGRF(CLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RV1126_PMUGRF_SOC_CON0, 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RV1126_PMU_CLKSEL_CON(5), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) &rv1126_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RV1126_MODE_CON, 10, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RV1126_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) RV1126_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RV1126_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RV1126_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RV1126_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RV1126_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RV1126_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RV1126_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RV1126_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RV1126_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RV1126_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* aclk_dmac is controlled by sgrf_clkgat_con. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RV1126_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RV1126_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RV1126_CLKGATE_CON(6), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RV1126_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RV1126_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) RV1126_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RV1126_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RV1126_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RV1126_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RV1126_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RV1126_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) RV1126_CLKSEL_CON(11), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RV1126_CLKGATE_CON(5), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &rv1126_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RV1126_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RV1126_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RV1126_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RV1126_CLKSEL_CON(13), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) RV1126_CLKGATE_CON(5), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &rv1126_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RV1126_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RV1126_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RV1126_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RV1126_CLKSEL_CON(15), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RV1126_CLKGATE_CON(5), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &rv1126_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RV1126_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) RV1126_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RV1126_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RV1126_CLKGATE_CON(5), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &rv1126_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RV1126_CLKGATE_CON(5), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RV1126_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) RV1126_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RV1126_CLKGATE_CON(6), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &rv1126_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RV1126_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) RV1126_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RV1126_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RV1126_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RV1126_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RV1126_CLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RV1126_CLKGATE_CON(3), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) RV1126_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RV1126_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RV1126_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RV1126_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RV1126_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RV1126_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) RV1126_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) RV1126_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) RV1126_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RV1126_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RV1126_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) RV1126_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) RV1126_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RV1126_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RV1126_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) RV1126_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RV1126_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RV1126_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) RV1126_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RV1126_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) RV1126_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RV1126_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) RV1126_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) RV1126_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RV1126_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RV1126_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RV1126_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RV1126_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RV1126_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RV1126_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RV1126_CLKGATE_CON(24), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RV1126_CLKGATE_CON(24), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RV1126_CLKGATE_CON(24), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RV1126_CLKGATE_CON(24), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) RV1126_CLKGATE_CON(24), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) RV1126_CLKGATE_CON(24), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* PD_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) COMPOSITE(ACLK_PDCRYPTO, "aclk_pdcrypto", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RV1126_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RV1126_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) COMPOSITE_NOMUX(HCLK_PDCRYPTO, "hclk_pdcrypto", "aclk_pdcrypto", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RV1126_CLKSEL_CON(4), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RV1126_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_pdcrypto", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RV1126_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_pdcrypto", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RV1126_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) COMPOSITE(CLK_CRYPTO_CORE, "aclk_crypto_core", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RV1126_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RV1126_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) COMPOSITE(CLK_CRYPTO_PKA, "aclk_crypto_pka", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RV1126_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RV1126_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* PD_AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RV1126_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RV1126_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RV1126_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RV1126_CLKSEL_CON(28), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RV1126_CLKGATE_CON(9), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &rv1126_i2s0_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RV1126_CLKGATE_CON(9), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) RV1126_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RV1126_CLKSEL_CON(29), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) RV1126_CLKGATE_CON(9), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &rv1126_i2s0_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RV1126_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RV1126_CLKGATE_CON(9), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RV1126_CLKGATE_CON(9), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RV1126_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) RV1126_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RV1126_CLKSEL_CON(32), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RV1126_CLKGATE_CON(10), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) &rv1126_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RV1126_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RV1126_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RV1126_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RV1126_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RV1126_CLKSEL_CON(34), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RV1126_CLKGATE_CON(10), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) &rv1126_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RV1126_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RV1126_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RV1126_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RV1126_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) RV1126_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RV1126_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) RV1126_CLKSEL_CON(37), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) RV1126_CLKGATE_CON(10), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) &rv1126_audpwm_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RV1126_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) RV1126_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RV1126_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RV1126_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RV1126_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Clock-Architecture Diagram 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* PD_VEPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) COMPOSITE(ACLK_PDVEPU, "aclk_pdvepu", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RV1126_CLKSEL_CON(40), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) RV1126_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) COMPOSITE_NOMUX(HCLK_PDVEPU, "hclk_pdvepu", "aclk_pdvepu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RV1126_CLKSEL_CON(41), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) RV1126_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GATE(ACLK_VENC, "aclk_venc", "aclk_pdvepu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) RV1126_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GATE(HCLK_VENC, "hclk_venc", "hclk_pdvepu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) RV1126_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) COMPOSITE(CLK_VENC_CORE, "clk_venc_core", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) RV1126_CLKSEL_CON(40), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) RV1126_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Clock-Architecture Diagram 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* PD_VDPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #if IS_ENABLED(CONFIG_ROCKCHIP_MPP_VDPU2) || IS_ENABLED(CONFIG_ROCKCHIP_MPP_RKVDEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RV1126_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) RV1126_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RV1126_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) RV1126_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) RV1126_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RV1126_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RV1126_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) RV1126_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) COMPOSITE(ACLK_PDVDEC, "aclk_pdvdec", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) RV1126_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RV1126_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) COMPOSITE_NOMUX(HCLK_PDVDEC, "hclk_pdvdec", "aclk_pdvdec", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) RV1126_CLKSEL_CON(41), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RV1126_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE(0, "aclk_pdvdec_niu", "aclk_pdvdec", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RV1126_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GATE(0, "hclk_pdvdec_niu", "hclk_pdvdec", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RV1126_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) COMPOSITE(ACLK_PDJPEG, "aclk_pdjpeg", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RV1126_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RV1126_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) COMPOSITE_NOMUX(HCLK_PDJPEG, "hclk_pdjpeg", "aclk_pdjpeg", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RV1126_CLKSEL_CON(44), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) RV1126_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(0, "aclk_pdjpeg_niu", "aclk_pdjpeg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RV1126_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(0, "hclk_pdjpeg_niu", "hclk_pdjpeg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) RV1126_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GATE(ACLK_VDEC, "aclk_vdec", "aclk_pdvdec", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RV1126_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) GATE(HCLK_VDEC, "hclk_vdec", "hclk_pdvdec", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) RV1126_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) COMPOSITE(CLK_VDEC_CORE, "clk_vdec_core", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) RV1126_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) RV1126_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) COMPOSITE(CLK_VDEC_CA, "clk_vdec_ca", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) RV1126_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) RV1126_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) COMPOSITE(CLK_VDEC_HEVC_CA, "clk_vdec_hevc_ca", mux_cpll_hpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) RV1126_CLKSEL_CON(43), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RV1126_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) GATE(ACLK_JPEG, "aclk_jpeg", "aclk_pdjpeg", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RV1126_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE(HCLK_JPEG, "hclk_jpeg", "hclk_pdjpeg", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RV1126_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RV1126_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RV1126_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) RV1126_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) RV1126_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RV1126_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RV1126_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) RV1126_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) RV1126_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) RV1126_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) RV1126_CLKSEL_CON(48), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) RV1126_CLKGATE_CON(14), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &rv1126_dclk_vop_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RV1126_CLKGATE_CON(14), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RV1126_CLKGATE_CON(14), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RV1126_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RV1126_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) RV1126_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Clock-Architecture Diagram 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) COMPOSITE(ACLK_PDVI_DIV, "aclk_pdvi_div", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) RV1126_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) RV1126_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) COMPOSITE_HALFDIV_OFFSET(ACLK_PDVI_NP5, "aclk_pdvi_np5", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) RV1126_CLKSEL_CON(49), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RV1126_CLKSEL_CON(76), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) RV1126_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MUX(ACLK_PDVI, "aclk_pdvi", mux_aclk_pdvi_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RV1126_CLKSEL_CON(76), 5, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) COMPOSITE_NOMUX(HCLK_PDVI, "hclk_pdvi", "aclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) RV1126_CLKSEL_CON(49), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RV1126_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) COMPOSITE_NOMUX(PCLK_PDVI, "pclk_pdvi", "aclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RV1126_CLKSEL_CON(50), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) RV1126_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) GATE(ACLK_ISP, "aclk_isp", "aclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) RV1126_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE(HCLK_ISP, "hclk_isp", "hclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RV1126_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) COMPOSITE(CLK_ISP_DIV, "clk_isp_div", mux_gpll_cpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) RV1126_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) RV1126_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) COMPOSITE_HALFDIV_OFFSET(CLK_ISP_NP5, "clk_isp_np5", mux_gpll_cpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) RV1126_CLKSEL_CON(50), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) RV1126_CLKSEL_CON(76), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RV1126_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MUX(CLK_ISP, "clk_isp", mux_clk_isp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) RV1126_CLKSEL_CON(76), 13, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) GATE(ACLK_CIF, "aclk_cif", "aclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RV1126_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GATE(HCLK_CIF, "hclk_cif", "hclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RV1126_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) COMPOSITE(DCLK_CIF, "dclk_cif", mux_gpll_cpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) RV1126_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) RV1126_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) COMPOSITE(CLK_CIF_OUT_DIV, "clk_cif_out2io_div", mux_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RV1126_CLKSEL_CON(51), 15, 1, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) RV1126_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) COMPOSITE_FRACMUX(CLK_CIF_OUT_FRACDIV, "clk_cif_out2io_fracdiv", "clk_cif_out2io_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RV1126_CLKSEL_CON(52), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) RV1126_CLKGATE_CON(15), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) &rv1126_cif_out2io_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) GATE(CLK_CIF_OUT, "clk_cif_out2io", "clk_cif_out2io_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) RV1126_CLKGATE_CON(15), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) COMPOSITE(CLK_MIPICSI_OUT_DIV, "clk_mipicsi_out2io_div", mux_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RV1126_CLKSEL_CON(73), 8, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RV1126_CLKGATE_CON(23), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) COMPOSITE_FRACMUX(CLK_MIPICSI_OUT_FRACDIV, "clk_mipicsi_out2io_fracdiv", "clk_mipicsi_out2io_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RV1126_CLKSEL_CON(74), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) RV1126_CLKGATE_CON(23), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &rv1126_mipicsi_out2io_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE(CLK_MIPICSI_OUT, "clk_mipicsi_out2io", "clk_mipicsi_out2io_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RV1126_CLKGATE_CON(23), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GATE(PCLK_CSIHOST, "pclk_csihost", "pclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RV1126_CLKGATE_CON(15), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(ACLK_CIFLITE, "aclk_ciflite", "aclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RV1126_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(HCLK_CIFLITE, "hclk_ciflite", "hclk_pdvi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RV1126_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) COMPOSITE(DCLK_CIFLITE, "dclk_ciflite", mux_gpll_cpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) RV1126_CLKSEL_CON(54), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) RV1126_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * Clock-Architecture Diagram 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* PD_ISPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) COMPOSITE(ACLK_PDISPP_DIV, "aclk_pdispp_div", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RV1126_CLKSEL_CON(68), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RV1126_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) COMPOSITE_HALFDIV_OFFSET(ACLK_PDISPP_NP5, "aclk_pdispp_np5", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) RV1126_CLKSEL_CON(68), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) RV1126_CLKSEL_CON(77), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RV1126_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) MUX(ACLK_PDISPP, "aclk_pdispp", mux_aclk_pdispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RV1126_CLKSEL_CON(77), 5, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) COMPOSITE_NOMUX(HCLK_PDISPP, "hclk_pdispp", "aclk_pdispp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RV1126_CLKSEL_CON(69), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RV1126_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GATE(ACLK_ISPP, "aclk_ispp", "aclk_pdispp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RV1126_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GATE(HCLK_ISPP, "hclk_ispp", "hclk_pdispp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RV1126_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) COMPOSITE(CLK_ISPP_DIV, "clk_ispp_div", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RV1126_CLKSEL_CON(69), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RV1126_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) COMPOSITE_HALFDIV_OFFSET(CLK_ISPP_NP5, "clk_ispp_np5", mux_cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RV1126_CLKSEL_CON(69), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) RV1126_CLKSEL_CON(77), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RV1126_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) MUX(CLK_ISPP, "clk_ispp", mux_clk_ispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) RV1126_CLKSEL_CON(77), 13, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * Clock-Architecture Diagram 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* PD_PHP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) RV1126_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RV1126_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* PD_SDCARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RV1126_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) RV1126_CLKGATE_CON(18), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* PD_SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) RV1126_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) RV1126_CLKGATE_CON(18), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) RV1126_CLKGATE_CON(18), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* PD_NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) RV1126_CLKGATE_CON(18), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) RV1126_CLKGATE_CON(18), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) RV1126_CLKGATE_CON(18), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) RV1126_CLKGATE_CON(18), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) RV1126_CLKGATE_CON(18), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) RV1126_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) RV1126_CLKGATE_CON(18), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) RV1126_CLKGATE_CON(18), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* PD_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) RV1126_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) RV1126_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RV1126_CLKGATE_CON(19), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) RV1126_CLKGATE_CON(19), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #if IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) || IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) RV1126_CLKGATE_CON(19), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) RV1126_CLKGATE_CON(19), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) RV1126_CLKGATE_CON(19), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) RV1126_CLKGATE_CON(19), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) RV1126_CLKGATE_CON(20), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) RV1126_CLKGATE_CON(20), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) RV1126_CLKGATE_CON(20), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) RV1126_CLKGATE_CON(20), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) RV1126_CLKGATE_CON(20), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) RV1126_CLKGATE_CON(20), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) RV1126_GMAC_CON, 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) RV1126_CLKGATE_CON(20), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) RV1126_GMAC_CON, 5, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) RV1126_CLKGATE_CON(20), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) RV1126_CLKGATE_CON(20), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) RV1126_CLKGATE_CON(20), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) RV1126_GMAC_CON, 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) RV1126_GMAC_CON, 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) RV1126_CLKGATE_CON(20), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) RV1126_CLKGATE_CON(20), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Clock-Architecture Diagram 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* PD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) COMPOSITE(ACLK_PDNPU_DIV, "aclk_pdnpu_div", mux_gpll_cpll_apll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) RV1126_CLKGATE_CON(22), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) COMPOSITE_HALFDIV(ACLK_PDNPU_NP5, "aclk_pdnpu_np5", mux_gpll_cpll_apll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) RV1126_CLKSEL_CON(65), 8, 2, MFLAGS, 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) RV1126_CLKGATE_CON(22), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MUX(ACLK_PDNPU, "aclk_pdnpu", mux_aclk_pdnpu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) RV1126_CLKSEL_CON(65), 12, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) COMPOSITE_NOMUX(HCLK_PDNPU, "hclk_pdnpu", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) RV1126_CLKSEL_CON(66), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) RV1126_CLKGATE_CON(22), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) COMPOSITE_NOMUX(PCLK_PDNPU, "pclk_pdnpu", "hclk_pdnpu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) RV1126_CLKSEL_CON(66), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) RV1126_CLKGATE_CON(22), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) GATE(ACLK_NPU, "aclk_npu", "aclk_pdnpu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) RV1126_CLKGATE_CON(22), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE(HCLK_NPU, "hclk_npu", "hclk_pdnpu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) RV1126_CLKGATE_CON(22), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) COMPOSITE(CLK_NPU_DIV, "clk_npu_div", mux_gpll_cpll_apll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) RV1126_CLKGATE_CON(22), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", mux_gpll_cpll_apll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) RV1126_CLKGATE_CON(22), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) MUX(CLK_CORE_NPU, "clk_core_npu", mux_clk_npu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) RV1126_CLKSEL_CON(67), 12, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) GATE(CLK_CORE_NPUPVTM, "clk_core_npupvtm", "clk_core_npu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) RV1126_CLKGATE_CON(22), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GATE(CLK_NPUPVTM, "clk_npupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) RV1126_CLKGATE_CON(22), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) GATE(PCLK_NPUPVTM, "pclk_npupvtm", "pclk_pdnpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) RV1126_CLKGATE_CON(22), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * Clock-Architecture Diagram 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) RV1126_CLKGATE_CON(23), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) RV1126_CLKGATE_CON(23), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) RV1126_CLKGATE_CON(23), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RV1126_CLKGATE_CON(23), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) RV1126_CLKGATE_CON(19), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) RV1126_CLKGATE_CON(19), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) RV1126_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) RV1126_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) RV1126_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) RV1126_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) RV1126_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) RV1126_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) RV1126_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) RV1126_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) RV1126_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) RV1126_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) RV1126_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) RV1126_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) RV1126_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) RV1126_CLKGATE_CON(6), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) RV1126_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) RV1126_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) RV1126_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* PD_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) GATE(0, "aclk_pdcrypto_niu", "aclk_pdcrypto", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) RV1126_CLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) GATE(0, "hclk_pdcrypto_niu", "hclk_pdcrypto", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) RV1126_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* PD_AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) RV1126_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) RV1126_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * Clock-Architecture Diagram 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* PD_VEPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) GATE(0, "aclk_pdvepu_niu", "aclk_pdvepu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) RV1126_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) GATE(0, "hclk_pdvepu_niu", "hclk_pdvepu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) RV1126_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) RV1126_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) RV1126_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) RV1126_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * Clock-Architecture Diagram 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GATE(0, "aclk_pdvi_niu", "aclk_pdvi", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) RV1126_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) GATE(0, "hclk_pdvi_niu", "hclk_pdvi", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) RV1126_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) GATE(0, "pclk_pdvi_niu", "pclk_pdvi", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RV1126_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * Clock-Architecture Diagram 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* PD_ISPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) GATE(0, "aclk_pdispp_niu", "aclk_pdispp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) RV1126_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) GATE(0, "hclk_pdispp_niu", "hclk_pdispp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) RV1126_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Clock-Architecture Diagram 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* PD_PHP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) RV1126_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) RV1126_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) RV1126_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) RV1126_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* PD_SDCARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RV1126_CLKGATE_CON(17), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* PD_SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) RV1126_CLKGATE_CON(17), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* PD_NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) RV1126_CLKGATE_CON(18), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* PD_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) RV1126_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) RV1126_CLKGATE_CON(19), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) RV1126_CLKGATE_CON(20), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) RV1126_CLKGATE_CON(20), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Clock-Architecture Diagram 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RV1126_CLKGATE_CON(21), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) RV1126_CLKGATE_CON(21), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) RV1126_CLKGATE_CON(21), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) RV1126_CLKGATE_CON(21), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) RV1126_CLKGATE_CON(23), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) RV1126_CLKGATE_CON(21), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) RV1126_CLKGATE_CON(21), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) RV1126_CLKGATE_CON(21), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) RV1126_CLKGATE_CON(21), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) RV1126_CLKGATE_CON(21), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) RV1126_CLKGATE_CON(21), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) RV1126_CLKGATE_CON(21), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) RV1126_CLKGATE_CON(21), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) RV1126_CLKGATE_CON(20), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) RV1126_CLKGATE_CON(21), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * Clock-Architecture Diagram 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* PD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) GATE(0, "aclk_pdnpu_niu", "aclk_pdnpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) RV1126_CLKGATE_CON(22), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) GATE(0, "hclk_pdnpu_niu", "hclk_pdnpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) RV1126_CLKGATE_CON(22), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GATE(0, "pclk_pdnpu_niu", "pclk_pdnpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) RV1126_CLKGATE_CON(22), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * Clock-Architecture Diagram 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) RV1126_CLKGATE_CON(23), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) RV1126_CLKGATE_CON(23), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) RV1126_CLKGATE_CON(23), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) RV1126_CLKGATE_CON(23), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) RV1126_CLKGATE_CON(23), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static void __iomem *rv1126_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void __iomem *rv1126_pmucru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) void rv1126_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (rv1126_pmucru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pr_warn("PMU CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) 32, 4, rv1126_pmucru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) 0x248, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (rv1126_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) 32, 4, rv1126_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) 0x588, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) EXPORT_SYMBOL_GPL(rv1126_dump_cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int rv1126_clk_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) rv1126_dump_cru();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct notifier_block rv1126_clk_panic_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .notifier_call = rv1126_clk_panic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static struct rockchip_clk_provider *pmucru_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static void __init rv1126_pmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) pr_err("%s: could not map cru pmu region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) rv1126_pmucru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) pr_err("%s: rockchip pmu clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ARRAY_SIZE(rv1126_pmu_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) RV1126_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ARRAY_SIZE(rv1126_clk_pmu_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pmucru_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static void __init rv1126_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct clk **cru_clks, **pmucru_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) rv1126_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) cru_clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pmucru_clks = pmucru_ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) rockchip_clk_register_plls(ctx, rv1126_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ARRAY_SIZE(rv1126_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) RV1126_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) 3, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) &rv1126_cpuclk_data, rv1126_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ARRAY_SIZE(rv1126_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) rockchip_clk_register_branches(ctx, rv1126_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ARRAY_SIZE(rv1126_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) &rv1126_clk_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct clk_rv1126_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static const struct clk_rv1126_inits clk_rv1126_pmu_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .inits = rv1126_pmu_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const struct clk_rv1126_inits clk_rv1126_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .inits = rv1126_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const struct of_device_id clk_rv1126_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .compatible = "rockchip,rv1126-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .data = &clk_rv1126_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .compatible = "rockchip,rv1126-pmucru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .data = &clk_rv1126_pmu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MODULE_DEVICE_TABLE(of, clk_rv1126_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int __init clk_rv1126_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) const struct clk_rv1126_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) match = of_match_device(clk_rv1126_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static struct platform_driver clk_rv1126_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "clk-rv1126",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .of_match_table = clk_rv1126_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) builtin_platform_driver_probe(clk_rv1126_driver, clk_rv1126_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MODULE_DESCRIPTION("Rockchip RV1126 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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