^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Shawn Lin <shawn.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Andy Yan <andy.yan@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/rv1108-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RV1108_GRF_SOC_STATUS0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum rv1108_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) apll, dpll, gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RV1108_DIV_CORE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RV1108_DIV_CORE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RV1108_CLKSEL0(_core_peri_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg = RV1108_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RV1108_DIV_CORE_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RV1108_CLKSEL0(_core_peri_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RV1108_CPUCLK_RATE(1608000000, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RV1108_CPUCLK_RATE(1512000000, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RV1108_CPUCLK_RATE(1488000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RV1108_CPUCLK_RATE(1416000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RV1108_CPUCLK_RATE(1392000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RV1108_CPUCLK_RATE(1296000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RV1108_CPUCLK_RATE(1200000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RV1108_CPUCLK_RATE(1104000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RV1108_CPUCLK_RATE(1008000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RV1108_CPUCLK_RATE(912000000, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RV1108_CPUCLK_RATE(816000000, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RV1108_CPUCLK_RATE(696000000, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RV1108_CPUCLK_RATE(600000000, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RV1108_CPUCLK_RATE(500000000, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RV1108_CPUCLK_RATE(408000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RV1108_CPUCLK_RATE(312000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RV1108_CPUCLK_RATE(216000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RV1108_CPUCLK_RATE(96000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .core_reg[0] = RV1108_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .mux_core_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PNAME(mux_pll_p) = { "xin24m", "xin24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) RV1108_PLL_CON(11), 8, 1, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RV1108_MISC_CON, 13, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RV1108_MISC_CON, 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RV1108_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) RV1108_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) RV1108_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RV1108_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) RV1108_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) RV1108_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) RV1108_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* PD_RKVENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RV1108_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RV1108_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) RV1108_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RV1108_CLKGATE_CON(19), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RV1108_CLKGATE_CON(19), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RV1108_CLKGATE_CON(19), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RV1108_CLKGATE_CON(19), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* PD_RKVDEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) RV1108_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) RV1108_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) RV1108_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) RV1108_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) RV1108_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) RV1108_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RV1108_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RV1108_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RV1108_CLKGATE_CON(19), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RV1108_CLKGATE_CON(19), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RV1108_CLKGATE_CON(19), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) RV1108_CLKGATE_CON(19), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PD_PMU_wrapper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) RV1108_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RV1108_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RV1108_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RV1108_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RV1108_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RV1108_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RV1108_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RV1108_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) RV1108_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) RV1108_CLKGATE_CON(8), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RV1108_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RV1108_CLKGATE_CON(9), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RV1108_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) RV1108_CLKGATE_CON(9), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RV1108_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RV1108_CLKGATE_CON(14), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RV1108_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) RV1108_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RV1108_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RV1108_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RV1108_CLKGATE_CON(17), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RV1108_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RV1108_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RV1108_CLKGATE_CON(17), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RV1108_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RV1108_CLKGATE_CON(17), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RV1108_CLKGATE_CON(17), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RV1108_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RV1108_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* PD_DSP_wrapper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RV1108_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RV1108_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RV1108_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RV1108_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RV1108_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RV1108_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RV1108_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RV1108_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) RV1108_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RV1108_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RV1108_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RV1108_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) RV1108_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RV1108_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) RV1108_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RV1108_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RV1108_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RV1108_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) RV1108_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RV1108_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RV1108_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RV1108_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RV1108_CLKGATE_CON(16), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) RV1108_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RV1108_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RV1108_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RV1108_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RV1108_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) RV1108_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RV1108_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RV1108_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RV1108_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) INVERTER(0, "pclk_vip", "ext_vip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) RV1108_CLKSEL_CON(31), 8, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RV1108_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RV1108_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RV1108_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RV1108_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RV1108_CLKGATE_CON(18), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RV1108_CLKGATE_CON(18), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RV1108_CLKGATE_CON(18), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RV1108_CLKGATE_CON(18), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RV1108_CLKGATE_CON(18), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RV1108_CLKGATE_CON(18), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RV1108_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RV1108_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RV1108_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RV1108_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) RV1108_CLKGATE_CON(18), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RV1108_CLKGATE_CON(18), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RV1108_CLKGATE_CON(18), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RV1108_CLKGATE_CON(18), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RV1108_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RV1108_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RV1108_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RV1108_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RV1108_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RV1108_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RV1108_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RV1108_CLKGATE_CON(2), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &rv1108_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RV1108_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RV1108_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RV1108_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) RK2928_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RK2928_CLKGATE_CON(2), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &rv1108_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RV1108_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RV1108_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) RV1108_CLKSEL_CON(10), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RV1108_CLKGATE_CON(2), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &rv1108_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) RV1108_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RV1108_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE(0, "aclk_bus_src_apll", "apll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RV1108_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RV1108_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RV1108_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RV1108_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) RV1108_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RV1108_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) RV1108_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) RV1108_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) RV1108_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) RV1108_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RV1108_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) RV1108_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RV1108_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RV1108_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RV1108_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RV1108_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RV1108_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RV1108_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RV1108_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) RV1108_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RV1108_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) RV1108_CLKSEL_CON(16), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RV1108_CLKGATE_CON(3), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &rv1108_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RV1108_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RV1108_CLKGATE_CON(3), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &rv1108_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RV1108_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) RV1108_CLKGATE_CON(3), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &rv1108_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RV1108_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) RV1108_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) RV1108_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) RV1108_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) RV1108_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RV1108_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RV1108_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) RV1108_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RV1108_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RV1108_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RV1108_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) RV1108_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RV1108_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) RV1108_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RV1108_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) RV1108_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) RV1108_CLKGATE_CON(12), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RV1108_CLKGATE_CON(12), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) RV1108_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RV1108_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RV1108_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RV1108_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RV1108_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) RV1108_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RV1108_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RV1108_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RV1108_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RV1108_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RV1108_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RV1108_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) RV1108_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RV1108_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RV1108_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RV1108_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RV1108_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RV1108_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RV1108_CLKGATE_CON(15), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RV1108_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RV1108_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RV1108_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RV1108_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RV1108_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RV1108_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RV1108_CLKSEL_CON(25), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RV1108_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) RV1108_CLKSEL_CON(26), 0, 8, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RV1108_CLKSEL_CON(25), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RV1108_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RV1108_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) RV1108_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RV1108_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void __iomem *rv1108_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static void rv1108_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (rv1108_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 32, 4, rv1108_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0x1f8, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static void __init rv1108_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rockchip_clk_register_plls(ctx, rv1108_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ARRAY_SIZE(rv1108_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RV1108_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rockchip_clk_register_branches(ctx, rv1108_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ARRAY_SIZE(rv1108_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 3, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &rv1108_cpuclk_data, rv1108_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ARRAY_SIZE(rv1108_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!rk_dump_cru) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) rv1108_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rk_dump_cru = rv1108_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int __init clk_rv1108_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rv1108_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const struct of_device_id clk_rv1108_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .compatible = "rockchip,rv1108-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_DEVICE_TABLE(of, clk_rv1108_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static struct platform_driver clk_rv1108_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = "clk-rv1108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .of_match_table = clk_rv1108_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) builtin_platform_driver_probe(clk_rv1108_driver, clk_rv1108_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_DESCRIPTION("Rockchip RV1108 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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