^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/rv1106-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CRU_PVTPLL0_CON0_L 0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CRU_PVTPLL0_CON0_H 0x11004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CRU_PVTPLL0_CON1_L 0x11008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CRU_PVTPLL0_CON1_H 0x1100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CRU_PVTPLL0_CON2_L 0x11010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CRU_PVTPLL0_CON2_H 0x11014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CRU_PVTPLL0_CON3_L 0x11018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CRU_PVTPLL0_CON3_H 0x1101c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CRU_PVTPLL0_OSC_CNT 0x11020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CRU_PVTPLL0_OSC_CNT_AVG 0x11024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRU_PVTPLL1_CON0_L 0x11030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRU_PVTPLL1_CON0_H 0x11034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CRU_PVTPLL1_CON1_L 0x11038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRU_PVTPLL1_CON1_H 0x1103c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRU_PVTPLL1_CON2_L 0x11040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CRU_PVTPLL1_CON2_H 0x11044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CRU_PVTPLL1_CON3_L 0x11048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CRU_PVTPLL1_CON3_H 0x1104c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CRU_PVTPLL1_OSC_CNT 0x11050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CRU_PVTPLL1_OSC_CNT_AVG 0x11054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RV1106_GRF_SOC_STATUS0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPU_PVTPLL_CON0_L 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPU_PVTPLL_CON0_H 0x40004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPU_PVTPLL_CON1 0x40008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPU_PVTPLL_CON2 0x4000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPU_PVTPLL_CON3 0x40010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPU_PVTPLL_OSC_CNT 0x40018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPU_PVTPLL_OSC_CNT_AVG 0x4001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PVTPLL_RING_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PVTPLL_RING_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PVTPLL_EN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PVTPLL_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PVTPLL_LENGTH_SEL_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PVTPLL_LENGTH_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CPU_CLK_PATH_BASE (0x18300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CPU_PVTPLL_PATH_CORE ((1 << 12) | (1 << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RV1106_FRAC_MAX_PRATE 1200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum rv1106_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) apll, dpll, cpll, gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RV1106_DIV_ACLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RV1106_DIV_ACLK_CORE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RV1106_DIV_PCLK_DBG_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RV1106_DIV_PCLK_DBG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RV1106_CORE_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RV1106_CORE_SEL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RV1106_ALT_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RV1106_ALT_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RV1106_CLKSEL0(_aclk_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg = RV1106_CORECLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .val = HIWORD_UPDATE(_aclk_core, RV1106_DIV_ACLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) RV1106_DIV_ACLK_CORE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RV1106_CLKSEL1(_pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .reg = RV1106_CORECLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .val = HIWORD_UPDATE(_pclk_dbg, RV1106_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) RV1106_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RV1106_CLKSEL2(_is_pvtpll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .reg = RV1106_CORECLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .val = HIWORD_UPDATE(_is_pvtpll, RV1106_CORE_SEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RV1106_CORE_SEL_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RV1106_CLKSEL3(_alt_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg = RV1106_CORECLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .val = HIWORD_UPDATE(_alt_div, RV1106_ALT_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) RV1106_ALT_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RV1106_CLKSEL0(_aclk_core), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) RV1106_CLKSEL1(_pclk_dbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pre_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RV1106_CLKSEL3(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RV1106_CLKSEL2(2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .post_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) RV1106_CLKSEL2(_is_pvtpll), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RV1106_CLKSEL3(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct rockchip_cpuclk_rate_table rv1106_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RV1106_CPUCLK_RATE(1608000000, 3, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RV1106_CPUCLK_RATE(1584000000, 3, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RV1106_CPUCLK_RATE(1560000000, 3, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RV1106_CPUCLK_RATE(1536000000, 3, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RV1106_CPUCLK_RATE(1512000000, 3, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RV1106_CPUCLK_RATE(1488000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RV1106_CPUCLK_RATE(1464000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RV1106_CPUCLK_RATE(1440000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RV1106_CPUCLK_RATE(1416000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RV1106_CPUCLK_RATE(1392000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) RV1106_CPUCLK_RATE(1368000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RV1106_CPUCLK_RATE(1344000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) RV1106_CPUCLK_RATE(1320000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) RV1106_CPUCLK_RATE(1296000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) RV1106_CPUCLK_RATE(1272000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) RV1106_CPUCLK_RATE(1248000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RV1106_CPUCLK_RATE(1224000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) RV1106_CPUCLK_RATE(1200000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RV1106_CPUCLK_RATE(1104000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) RV1106_CPUCLK_RATE(1096000000, 2, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RV1106_CPUCLK_RATE(1008000000, 1, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) RV1106_CPUCLK_RATE(912000000, 1, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RV1106_CPUCLK_RATE(816000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RV1106_CPUCLK_RATE(696000000, 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) RV1106_CPUCLK_RATE(600000000, 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) RV1106_CPUCLK_RATE(408000000, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) RV1106_CPUCLK_RATE(312000000, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) RV1106_CPUCLK_RATE(216000000, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RV1106_CPUCLK_RATE(96000000, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct rockchip_cpuclk_reg_data rv1106_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .core_reg[0] = RV1106_CORECLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mux_core_alt = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mux_core_main = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mux_core_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PNAME(mux_pll_p) = { "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PNAME(mux_24m_32k_p) = { "xin24m", "clk_rtc_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(mux_400m_300m_pvtpll0_pvtpll1_p) = { "clk_400m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PNAME(mux_500m_300m_pvtpll0_pvtpll1_p) = { "clk_500m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PNAME(mux_339m_200m_pvtpll0_pvtpll1_p) = { "clk_339m_src", "clk_200m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PNAME(mux_500m_300m_200m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PNAME(mux_50m_24m_p) = { "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PNAME(mux_400m_24m_p) = { "clk_400m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_pvtm_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PNAME(mux_200m_100m_24m_32k_p) = { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PNAME(mux_100m_pmu_24m_p) = { "clk_100m_pmu", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_pmu", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PNAME(mux_dpll_300m_p) = { "dpll", "clk_300m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PNAME(clk_ref_mipi0_p) = { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PNAME(clk_ref_mipi1_p) = { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PNAME(clk_vicap_m0_p) = { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PNAME(clk_vicap_m1_p) = { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct rockchip_pll_clock rv1106_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CLK_IGNORE_UNUSED, RV1106_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RV1106_MODE_CON, 0, 10, 0, rv1106_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0, RV1106_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RV1106_MODE_CON, 2, 10, 0, rv1106_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CLK_IGNORE_UNUSED, RV1106_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RV1106_SUBDDRMODE_CON, 0, 10, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0, RV1106_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RV1106_MODE_CON, 4, 10, 0, rv1106_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct rockchip_clk_branch rv1106_i2s0_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RV1106_CLKSEL_CON(19), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct rockchip_clk_branch rv1106_i2s0_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RV1106_CLKSEL_CON(21), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct rockchip_clk_branch rv1106_clk_ref_mipi0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX(CLK_REF_MIPI0, "clk_ref_mipi0", clk_ref_mipi0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RV1106_CLKSEL_CON(27), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct rockchip_clk_branch rv1106_clk_ref_mipi1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX(CLK_REF_MIPI1, "clk_ref_mipi1", clk_ref_mipi1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RV1106_CLKSEL_CON(29), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct rockchip_clk_branch rv1106_clk_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RV1106_CLKSEL_CON(7), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct rockchip_clk_branch rv1106_clk_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RV1106_CLKSEL_CON(9), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct rockchip_clk_branch rv1106_clk_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RV1106_CLKSEL_CON(11), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct rockchip_clk_branch rv1106_clk_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RV1106_CLKSEL_CON(13), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct rockchip_clk_branch rv1106_clk_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RV1106_CLKSEL_CON(15), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct rockchip_clk_branch rv1106_clk_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RV1106_CLKSEL_CON(17), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct rockchip_clk_branch rv1106_clk_vicap_m0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MUX(CLK_VICAP_M0, "clk_vicap_m0", clk_vicap_m0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RV1106_CLKSEL_CON(31), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct rockchip_clk_branch rv1106_clk_vicap_m1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MUX(CLK_VICAP_M1, "clk_vicap_m1", clk_vicap_m1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RV1106_CLKSEL_CON(33), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RV1106_CORECLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RV1106_CORECLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) COMPOSITE(HCLK_CPU, "hclk_cpu", mux_gpll_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) RV1106_CORECLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RV1106_CORECLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) COMPOSITE(CLK_CORE_MCU, "clk_core_mcu", mux_gpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) RV1106_CORECLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RV1106_CORECLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RV1106_CORECLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RV1106_CORECLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) GATE(0, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RV1106_CORECLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* PD _TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RV1106_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) COMPOSITE(CLK_100M_SRC, "clk_100m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RV1106_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) RV1106_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) COMPOSITE(CLK_150M_SRC, "clk_150m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) RV1106_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RV1106_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) COMPOSITE(CLK_200M_SRC, "clk_200m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RV1106_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RV1106_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) COMPOSITE(CLK_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RV1106_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RV1106_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) COMPOSITE(CLK_300M_SRC, "clk_300m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RV1106_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RV1106_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) COMPOSITE_HALFDIV(CLK_339M_SRC, "clk_339m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RV1106_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RV1106_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) COMPOSITE(CLK_400M_SRC, "clk_400m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RV1106_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) RV1106_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) RV1106_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RV1106_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) COMPOSITE(CLK_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RV1106_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RV1106_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RV1106_CLKSEL_CON(24), 5, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RV1106_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RV1106_CLKSEL_CON(17), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RV1106_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RV1106_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RV1106_CLKGATE_CON(1), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &rv1106_i2s0_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RV1106_CLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) RV1106_CLKSEL_CON(19), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RV1106_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RV1106_CLKSEL_CON(20), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RV1106_CLKGATE_CON(2), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) &rv1106_i2s0_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RV1106_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) RV1106_CLKSEL_CON(21), 2, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) COMPOSITE(CLK_REF_MIPI0_SRC, "clk_ref_mipi0_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RV1106_CLKSEL_CON(25), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RV1106_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) COMPOSITE_FRACMUX(CLK_REF_MIPI0_FRAC, "clk_ref_mipi0_frac", "clk_ref_mipi0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RV1106_CLKSEL_CON(26), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RV1106_CLKGATE_CON(3), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &rv1106_clk_ref_mipi0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RV1106_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) COMPOSITE(CLK_REF_MIPI1_SRC, "clk_ref_mipi1_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RV1106_CLKSEL_CON(27), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RV1106_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) COMPOSITE_FRACMUX(CLK_REF_MIPI1_FRAC, "clk_ref_mipi1_frac", "clk_ref_mipi1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RV1106_CLKSEL_CON(28), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RV1106_CLKGATE_CON(3), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &rv1106_clk_ref_mipi1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RV1106_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) COMPOSITE(CLK_UART0_SRC, "clk_uart0_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) RV1106_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RV1106_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RV1106_CLKSEL_CON(6), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RV1106_CLKGATE_CON(0), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &rv1106_clk_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) RV1106_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RV1106_CLKSEL_CON(7), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RV1106_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RV1106_CLKSEL_CON(8), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RV1106_CLKGATE_CON(0), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &rv1106_clk_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RV1106_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RV1106_CLKSEL_CON(9), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RV1106_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RV1106_CLKSEL_CON(10), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RV1106_CLKGATE_CON(1), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &rv1106_clk_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RV1106_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RV1106_CLKSEL_CON(11), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RV1106_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RV1106_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RV1106_CLKGATE_CON(1), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &rv1106_clk_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RV1106_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RV1106_CLKSEL_CON(13), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RV1106_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RV1106_CLKSEL_CON(14), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RV1106_CLKGATE_CON(1), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &rv1106_clk_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RV1106_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RV1106_CLKSEL_CON(15), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RV1106_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RV1106_CLKSEL_CON(16), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) RV1106_CLKGATE_CON(1), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &rv1106_clk_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RV1106_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) COMPOSITE(CLK_VICAP_M0_SRC, "clk_vicap_m0_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RV1106_CLKSEL_CON(29), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RV1106_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) COMPOSITE_FRACMUX(CLK_VICAP_M0_FRAC, "clk_vicap_m0_frac", "clk_vicap_m0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RV1106_CLKSEL_CON(30), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RV1106_CLKGATE_CON(3), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &rv1106_clk_vicap_m0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RV1106_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RV1106_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RV1106_CLKSEL_CON(32), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RV1106_CLKGATE_CON(3), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &rv1106_clk_vicap_m1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RV1106_CLKGATE_CON(3), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) COMPOSITE(DCLK_VOP_SRC, "dclk_vop_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RV1106_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* PD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) RV1106_NPUCLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", mux_500m_300m_pvtpll0_pvtpll1_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RV1106_NPUCLKSEL_CON(0), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RV1106_NPUCLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RV1106_NPUCLKSEL_CON(0), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RV1106_NPUCLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) RV1106_NPUCLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) RV1106_NPUCLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) RV1106_PERICLKSEL_CON(1), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RV1106_PERICLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) RV1106_PERICLKSEL_CON(1), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RV1106_PERICLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) COMPOSITE_NODIV(HCLK_PERI_ROOT, "hclk_peri_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RV1106_PERICLKSEL_CON(1), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RV1106_PERICLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RV1106_PERICLKSEL_CON(9), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RV1106_PERICLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) RV1106_PERICLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RV1106_PERICLKSEL_CON(8), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RV1106_PERICLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RV1106_PERICLKSEL_CON(6), 5, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RV1106_PERICLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) RV1106_PERICLKSEL_CON(6), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RV1106_PERICLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RV1106_PERICLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RV1106_PERICLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) RV1106_PERICLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RV1106_PERICLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) COMPOSITE_NODIV(DCLK_DECOM, "dclk_decom", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) RV1106_PERICLKSEL_CON(7), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RV1106_PERICLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RV1106_PERICLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RV1106_PERICLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RV1106_PERICLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_400m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RV1106_PERICLKSEL_CON(7), 6, 1, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RV1106_PERICLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RV1106_PERICLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RV1106_PERICLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RV1106_PERICLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) RV1106_PERICLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RV1106_PERICLKSEL_CON(1), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RV1106_PERICLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) RV1106_PERICLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RV1106_PERICLKSEL_CON(1), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RV1106_PERICLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RV1106_PERICLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RV1106_PERICLKSEL_CON(1), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RV1106_PERICLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RV1106_PERICLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) RV1106_PERICLKSEL_CON(2), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) RV1106_PERICLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) RV1106_PERICLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) RV1106_PERICLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) RV1106_PERICLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RV1106_PERICLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RV1106_PERICLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) COMPOSITE_NODIV(CLK_PWM0_PERI, "clk_pwm0_peri", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) RV1106_PERICLKSEL_CON(11), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) RV1106_PERICLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RV1106_PERICLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) RV1106_PERICLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RV1106_PERICLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) COMPOSITE(SCLK_SFC, "sclk_sfc", mux_500m_300m_200m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RV1106_PERICLKSEL_CON(7), 12, 2, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) RV1106_PERICLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) RV1106_PERICLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RV1106_PERICLKGATE_CON(6), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RV1106_PERICLKGATE_CON(3), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RV1106_PERICLKSEL_CON(6), 9, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RV1106_PERICLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RV1106_PERICLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) RV1106_PERICLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) RV1106_PERICLKSEL_CON(6), 11, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RV1106_PERICLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) RV1106_PERICLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) RV1106_PERICLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) RV1106_PERICLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) RV1106_PERICLKGATE_CON(5), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RV1106_PERICLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RV1106_PERICLKSEL_CON(6), 0, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) RV1106_PERICLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RV1106_PERICLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RV1106_PERICLKSEL_CON(6), 3, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RV1106_PERICLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RV1106_PERICLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) RV1106_PERICLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RV1106_PERICLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) RV1106_PERICLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RV1106_PERICLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RV1106_PERICLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RV1106_PERICLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RV1106_PERICLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) RV1106_PERICLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RV1106_PERICLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RV1106_PERICLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) RV1106_PERICLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RV1106_PERICLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RV1106_PERICLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RV1106_PERICLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RV1106_PERICLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RV1106_PERICLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RV1106_PERICLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RV1106_PERICLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RV1106_PERICLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RV1106_PERICLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) RV1106_PERICLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RV1106_PERICLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RV1106_PERICLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* PD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RV1106_PMUCLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RV1106_PMUCLKGATE_CON(1), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &rv1106_rtc32k_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DIV(CLK_100M_PMU, "clk_100m_pmu", "clk_200m_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) RV1106_PMUCLKSEL_CON(0), 0, 3, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) COMPOSITE_NODIV(PCLK_PMU_ROOT, "pclk_pmu_root", mux_100m_pmu_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RV1106_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RV1106_PMUCLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) COMPOSITE_NODIV(HCLK_PMU_ROOT, "hclk_pmu_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RV1106_PMUCLKSEL_CON(0), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RV1106_PMUCLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RV1106_PMUCLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) RV1106_PMUCLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) RV1106_PMUCLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RV1106_PMUCLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RV1106_PMUCLKSEL_CON(0), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RV1106_PMUCLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RV1106_PMUCLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RV1106_PMUCLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RV1106_PMUCLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RV1106_PMUCLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RV1106_PMUCLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RV1106_PMUCLKSEL_CON(1), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RV1106_PMUCLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RV1106_PMUCLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) RV1106_PMUCLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RV1106_PMUCLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RV1106_PMUCLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RV1106_PMUCLKSEL_CON(7), 2, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RV1106_PMUCLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* PD_SUBDDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) COMPOSITE(CLK_CORE_DDRC_SRC, "clk_core_ddrc_src", mux_dpll_300m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RV1106_SUBDDRCLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RV1106_SUBDDRCLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RV1106_SUBDDRCLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RV1106_SUBDDRCLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RV1106_SUBDDRCLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RV1106_SUBDDRCLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) RV1106_SUBDDRCLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* PD_VEPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) COMPOSITE_NODIV(HCLK_VEPU_ROOT, "hclk_vepu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RV1106_VEPUCLKSEL_CON(0), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) RV1106_VEPUCLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) COMPOSITE_NODIV(ACLK_VEPU_COM_ROOT, "aclk_vepu_com_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) RV1106_VEPUCLKSEL_CON(0), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) RV1106_VEPUCLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RV1106_VEPUCLKSEL_CON(0), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) RV1106_VEPUCLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) COMPOSITE_NODIV(PCLK_VEPU_ROOT, "pclk_vepu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) RV1106_VEPUCLKSEL_CON(0), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) RV1106_VEPUCLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) RV1106_VEPUCLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RV1106_VEPUCLKSEL_CON(0), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) RV1106_VEPUCLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) RV1106_VEPUCLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) RV1106_VEPUCLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) RV1106_VEPUCLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", mux_400m_300m_pvtpll0_pvtpll1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RV1106_VEPUCLKSEL_CON(0), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) RV1106_VEPUCLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) COMPOSITE_NODIV(CLK_CORE_VEPU_DVBM, "clk_core_vepu_dvbm", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RV1106_VEPUCLKSEL_CON(0), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) RV1106_VEPUCLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) RV1106_VEPUCLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) RV1106_VEPUCLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) RV1106_VEPUCLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) RV1106_VEPUCLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RV1106_VICLKSEL_CON(0), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) RV1106_VICLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RV1106_VICLKSEL_CON(0), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RV1106_VICLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RV1106_VICLKSEL_CON(0), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) RV1106_VICLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) COMPOSITE_NODIV(PCLK_VI_RTC_ROOT, "pclk_vi_rtc_root", mux_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RV1106_VICLKSEL_CON(0), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RV1106_VICLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RV1106_VICLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RV1106_VICLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RV1106_VICLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RV1106_VICLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) RV1106_VICLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) RV1106_VICLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) COMPOSITE_NODIV(CLK_CORE_ISP3P2, "clk_core_isp3p2", mux_339m_200m_pvtpll0_pvtpll1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RV1106_VICLKSEL_CON(0), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RV1106_VICLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RV1106_VICLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", mux_400m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RV1106_VICLKSEL_CON(1), 14, 1, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) RV1106_VICLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RV1106_VICLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RV1106_VICLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RV1106_VICLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) RV1106_VICLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_339m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) RV1106_VICLKSEL_CON(0), 9, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) RV1106_VICLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) RV1106_VICLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) RV1106_VICLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) COMPOSITE_NODIV(ACLK_MAC_ROOT, "aclk_mac_root", mux_300m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) RV1106_VOCLKSEL_CON(1), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) RV1106_VOCLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) RV1106_VOCLKSEL_CON(0), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) RV1106_VOCLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RV1106_VOCLKSEL_CON(0), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) RV1106_VOCLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RV1106_VOCLKSEL_CON(0), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RV1106_VOCLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) COMPOSITE_NODIV(ACLK_VOP_ROOT, "aclk_vop_root", mux_300m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RV1106_VOCLKSEL_CON(1), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) RV1106_VOCLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RV1106_VOCLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RV1106_VOCLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RV1106_VOCLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RV1106_VOCLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FACTOR(CLK_GMAC0_50M_O, "clk_gmac0_50m_o", "clk_50m_src", 0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) FACTOR(CLK_GMAC0_REF_50M, "clk_gmac0_ref_50m", "clk_gmac0_50m_o", 0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DIV(CLK_GMAC0_TX_50M_O, "clk_gmac0_tx_50m_o", "clk_gmac0_50m_o", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) RV1106_VOCLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) RV1106_VOCLKSEL_CON(3), 10, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RV1106_VOCLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) RV1106_VOCLKSEL_CON(1), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) RV1106_VOCLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", mux_400m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) RV1106_VOCLKSEL_CON(2), 13, 1, MFLAGS, 7, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) RV1106_VOCLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) RV1106_VOCLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) RV1106_VOCLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RV1106_VOCLKSEL_CON(3), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) RV1106_VOCLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RV1106_VOCLKSEL_CON(3), 5, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) RV1106_VOCLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RV1106_VOCLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RV1106_VOCLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) RV1106_VOCLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* IO CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) RV1106_VICLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) RV1106_VICLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) RV1106_VICLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RV1106_VICLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) RV1106_VICLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RV1106_VICLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RV1106_VICLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) RV1106_VICLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static struct rockchip_clk_branch rv1106_grf_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_src_emmc", RV1106_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_src_emmc", RV1106_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc", RV1106_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc", RV1106_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RV1106_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RV1106_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static void __iomem *rv1106_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static struct rockchip_clk_provider *grf_ctx, *cru_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) void rv1106_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (rv1106_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) 32, 4, rv1106_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 0x588, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) EXPORT_SYMBOL_GPL(rv1106_dump_cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void _cru_pvtpll_calibrate(int count_offset, int length_offset, int target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int rate0, rate1, delta, length_ori, length, step, val, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) rate0 = readl_relaxed(rv1106_cru_base + count_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (rate0 < target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* delta < (3.125% * target_rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if ((rate0 - target_rate) < (target_rate >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) length_ori = readl_relaxed(rv1106_cru_base + length_offset) & PVTPLL_LENGTH_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) length = length_ori;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) length++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) writel_relaxed(val, rv1106_cru_base + length_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) rate1 = readl_relaxed(rv1106_cru_base + count_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if ((rate1 < target_rate) || (rate1 >= rate0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (abs(rate1 - target_rate) < (target_rate >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) step = rate0 - rate1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) delta = rate1 - target_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) length += delta / step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) writel_relaxed(val, rv1106_cru_base + length_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) rate0 = readl_relaxed(rv1106_cru_base + count_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) while (abs(rate0 - target_rate) >= (target_rate >> 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (i++ > 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (rate0 > target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) length++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (length <= length_ori)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) writel_relaxed(val, rv1106_cru_base + length_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) rate0 = readl_relaxed(rv1106_cru_base + count_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void _grf_pvtpll_calibrate(int count_offset, int length_offset, int target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned int rate0, rate1, delta, length_ori, length, step, val, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) regmap_read(cru_ctx->grf, count_offset, &rate0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (rate0 < target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* delta < (3.125% * target_rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if ((rate0 - target_rate) < (target_rate >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) regmap_read(cru_ctx->grf, length_offset, &length_ori);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) length = length_ori;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) length_ori = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) length &= PVTPLL_LENGTH_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) length++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) regmap_write(cru_ctx->grf, length_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) regmap_read(cru_ctx->grf, count_offset, &rate1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if ((rate1 < target_rate) || (rate1 >= rate0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (abs(rate1 - target_rate) < (target_rate >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) step = rate0 - rate1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) delta = rate1 - target_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) length += delta / step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) regmap_write(cru_ctx->grf, length_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) regmap_read(cru_ctx->grf, count_offset, &rate0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) while (abs(rate0 - target_rate) >= (target_rate >> 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (i++ > 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (rate0 > target_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) length++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (length <= length_ori)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) regmap_write(cru_ctx->grf, length_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) regmap_read(cru_ctx->grf, count_offset, &rate0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static void rockchip_rv1106_pvtpll_calibrate(struct work_struct *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) clk = __clk_lookup("clk_pvtpll_0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) _cru_pvtpll_calibrate(CRU_PVTPLL0_OSC_CNT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) CRU_PVTPLL0_CON0_H, rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) clk = __clk_lookup("clk_pvtpll_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) _cru_pvtpll_calibrate(CRU_PVTPLL1_OSC_CNT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) CRU_PVTPLL1_CON0_H, rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) clk = __clk_lookup("cpu_pvtpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) _grf_pvtpll_calibrate(CPU_PVTPLL_OSC_CNT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) CPU_PVTPLL_CON0_H, rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static DECLARE_DEFERRABLE_WORK(pvtpll_calibrate_work, rockchip_rv1106_pvtpll_calibrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* set pvtpll ref clk mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) regmap_write(ctx->grf, CPU_PVTPLL_CON0_H, HIWORD_UPDATE(0x6, PVTPLL_LENGTH_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PVTPLL_LENGTH_SEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PVTPLL_RING_SEL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) regmap_write(ctx->grf, CPU_PVTPLL_CON0_L, HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PVTPLL_EN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) schedule_delayed_work(&pvtpll_calibrate_work, msecs_to_jiffies(3000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int rv1106_clk_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) rv1106_dump_cru();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static struct notifier_block rv1106_clk_panic_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .notifier_call = rv1106_clk_panic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static void __init rv1106_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct clk **cru_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) rv1106_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) cru_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) rockchip_rv1106_pvtpll_init(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) cru_clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) rockchip_clk_register_plls(ctx, rv1106_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ARRAY_SIZE(rv1106_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) RV1106_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) 3, cru_clks[PLL_APLL], cru_clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) &rv1106_cpuclk_data, rv1106_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ARRAY_SIZE(rv1106_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rockchip_clk_register_branches(ctx, rv1106_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ARRAY_SIZE(rv1106_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) rockchip_clk_register_branches(grf_ctx, rv1106_grf_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ARRAY_SIZE(rv1106_grf_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) rockchip_register_softrst(np, 31745, reg_base + RV1106_PMUSOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) &rv1106_clk_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static void __init rv1106_grf_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) reg_base = of_iomap(of_get_parent(np), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pr_err("%s: could not map cru grf region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ctx = rockchip_clk_init(np, reg_base, CLK_NR_GRF_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pr_err("%s: rockchip grf clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) grf_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) CLK_OF_DECLARE(rv1106_grf_cru, "rockchip,rv1106-grf-cru", rv1106_grf_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct clk_rv1106_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const struct clk_rv1106_inits clk_rv1106_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .inits = rv1106_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const struct clk_rv1106_inits clk_rv1106_grf_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .inits = rv1106_grf_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const struct of_device_id clk_rv1106_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .compatible = "rockchip,rv1106-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .data = &clk_rv1106_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .compatible = "rockchip,rv1106-grf-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .data = &clk_rv1106_grf_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) MODULE_DEVICE_TABLE(of, clk_rv1106_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static int __init clk_rv1106_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) const struct clk_rv1106_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) match = of_match_device(clk_rv1106_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct platform_driver clk_rv1106_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .name = "clk-rv1106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .of_match_table = clk_rv1106_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) builtin_platform_driver_probe(clk_rv1106_driver, clk_rv1106_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) MODULE_DESCRIPTION("Rockchip RV1106 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #endif /* MODULE */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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