^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/rk3588-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3588_GRF_SOC_STATUS0 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3588_PHYREF_ALT_GATE 0xc38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3588_FRAC_MAX_PRATE 1500000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3588_DCLK_MAX_PRATE 594000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum rk3588_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* _mhz, _p, _m, _s, _k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RK3588_CLK_DSU_SEL_DF_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RK3588_CLK_DSU_SEL_DF_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RK3588_CLK_DSU_DF_SRC_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RK3588_CLK_DSU_DF_SRC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RK3588_CLK_DSU_DF_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RK3588_CLK_DSU_DF_DIV_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RK3588_ACLKM_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RK3588_ACLKM_DSU_DIV_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RK3588_ACLKS_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RK3588_ACLKS_DSU_DIV_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RK3588_ACLKMP_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RK3588_ACLKMP_DSU_DIV_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RK3588_PERIPH_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RK3588_PERIPH_DSU_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RK3588_ATCLK_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RK3588_ATCLK_DSU_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RK3588_GICCLK_DSU_DIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RK3588_GICCLK_DSU_DIV_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RK3588_CORE_B0_SEL(_apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RK3588_CORE_B1_SEL(_apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RK3588_CORE_B2_SEL(_apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RK3588_CORE_B3_SEL(_apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RK3588_CORE_L_SEL0(_offs, _apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg = RK3588_DSU_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RK3588_CLK_DSU_DF_SRC_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RK3588_CLK_DSU_DF_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reg = RK3588_DSU_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RK3588_ACLKM_DSU_DIV_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RK3588_ACLKMP_DSU_DIV_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RK3588_ACLKS_DSU_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RK3588_CORE_L_SEL3(_periph) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg = RK3588_DSU_CLKSEL_CON(2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RK3588_PERIPH_DSU_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RK3588_CORE_L_SEL4(_gicclk, _atclk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .reg = RK3588_DSU_CLKSEL_CON(3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) RK3588_GICCLK_DSU_DIV_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) RK3588_ATCLK_DSU_DIV_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .pre_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) RK3588_CORE_B0_SEL(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) RK3588_CORE_B1_SEL(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .post_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) RK3588_CORE_B0_SEL(_apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) RK3588_CORE_B1_SEL(_apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .pre_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) RK3588_CORE_B2_SEL(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK3588_CORE_B3_SEL(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .post_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) RK3588_CORE_B2_SEL(_apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RK3588_CORE_B3_SEL(_apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pre_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) RK3588_CORE_L_SEL0(0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RK3588_CORE_L_SEL0(1, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) RK3588_CORE_L_SEL1(3, 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RK3588_CORE_L_SEL2(2, 3, 3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) RK3588_CORE_L_SEL3(4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RK3588_CORE_L_SEL4(4, 4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .post_muxs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) RK3588_CORE_L_SEL0(0, _apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) RK3588_CORE_L_SEL0(1, _apllcore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RK3588_CORE_L_SEL1(_seldsu, _divdsu), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) RK3588_CPUB01CLK_RATE(2496000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) RK3588_CPUB01CLK_RATE(2400000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) RK3588_CPUB01CLK_RATE(2304000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) RK3588_CPUB01CLK_RATE(2208000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) RK3588_CPUB01CLK_RATE(2184000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) RK3588_CPUB01CLK_RATE(2088000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RK3588_CPUB01CLK_RATE(2040000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RK3588_CPUB01CLK_RATE(2016000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) RK3588_CPUB01CLK_RATE(1992000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RK3588_CPUB01CLK_RATE(1896000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RK3588_CPUB01CLK_RATE(1800000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RK3588_CPUB01CLK_RATE(1704000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RK3588_CPUB01CLK_RATE(1608000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RK3588_CPUB01CLK_RATE(1584000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) RK3588_CPUB01CLK_RATE(1560000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RK3588_CPUB01CLK_RATE(1536000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) RK3588_CPUB01CLK_RATE(1512000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) RK3588_CPUB01CLK_RATE(1488000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) RK3588_CPUB01CLK_RATE(1464000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) RK3588_CPUB01CLK_RATE(1440000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RK3588_CPUB01CLK_RATE(1416000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RK3588_CPUB01CLK_RATE(1392000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) RK3588_CPUB01CLK_RATE(1368000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) RK3588_CPUB01CLK_RATE(1344000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RK3588_CPUB01CLK_RATE(1320000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RK3588_CPUB01CLK_RATE(1296000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RK3588_CPUB01CLK_RATE(1272000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) RK3588_CPUB01CLK_RATE(1248000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RK3588_CPUB01CLK_RATE(1224000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) RK3588_CPUB01CLK_RATE(1200000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RK3588_CPUB01CLK_RATE(1104000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) RK3588_CPUB01CLK_RATE(1008000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RK3588_CPUB01CLK_RATE(912000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) RK3588_CPUB01CLK_RATE(816000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RK3588_CPUB01CLK_RATE(696000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) RK3588_CPUB01CLK_RATE(600000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RK3588_CPUB01CLK_RATE(408000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) RK3588_CPUB01CLK_RATE(312000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) RK3588_CPUB01CLK_RATE(216000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) RK3588_CPUB01CLK_RATE(96000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .div_core_shift[0] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .div_core_shift[1] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .div_core_mask[1] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .mux_core_main = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) RK3588_CPUB23CLK_RATE(2496000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) RK3588_CPUB23CLK_RATE(2400000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) RK3588_CPUB23CLK_RATE(2304000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RK3588_CPUB23CLK_RATE(2208000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) RK3588_CPUB23CLK_RATE(2184000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RK3588_CPUB23CLK_RATE(2088000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RK3588_CPUB23CLK_RATE(2040000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK3588_CPUB23CLK_RATE(2016000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) RK3588_CPUB23CLK_RATE(1992000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) RK3588_CPUB23CLK_RATE(1896000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RK3588_CPUB23CLK_RATE(1800000000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK3588_CPUB23CLK_RATE(1704000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) RK3588_CPUB23CLK_RATE(1608000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RK3588_CPUB23CLK_RATE(1584000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RK3588_CPUB23CLK_RATE(1560000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RK3588_CPUB23CLK_RATE(1536000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RK3588_CPUB23CLK_RATE(1512000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RK3588_CPUB23CLK_RATE(1488000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RK3588_CPUB23CLK_RATE(1464000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RK3588_CPUB23CLK_RATE(1440000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RK3588_CPUB23CLK_RATE(1416000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK3588_CPUB23CLK_RATE(1392000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK3588_CPUB23CLK_RATE(1368000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RK3588_CPUB23CLK_RATE(1344000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RK3588_CPUB23CLK_RATE(1320000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RK3588_CPUB23CLK_RATE(1296000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RK3588_CPUB23CLK_RATE(1272000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) RK3588_CPUB23CLK_RATE(1248000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK3588_CPUB23CLK_RATE(1224000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RK3588_CPUB23CLK_RATE(1200000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) RK3588_CPUB23CLK_RATE(1104000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RK3588_CPUB23CLK_RATE(1008000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) RK3588_CPUB23CLK_RATE(912000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RK3588_CPUB23CLK_RATE(816000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RK3588_CPUB23CLK_RATE(696000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RK3588_CPUB23CLK_RATE(600000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RK3588_CPUB23CLK_RATE(408000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RK3588_CPUB23CLK_RATE(312000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RK3588_CPUB23CLK_RATE(216000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RK3588_CPUB23CLK_RATE(96000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .div_core_shift[0] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .div_core_shift[1] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .div_core_mask[1] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .num_cores = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mux_core_main = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK3588_CPULCLK_RATE(2208000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RK3588_CPULCLK_RATE(2184000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RK3588_CPULCLK_RATE(2088000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RK3588_CPULCLK_RATE(2040000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK3588_CPULCLK_RATE(2016000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) RK3588_CPULCLK_RATE(1992000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RK3588_CPULCLK_RATE(1896000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) RK3588_CPULCLK_RATE(1800000000, 1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RK3588_CPULCLK_RATE(1704000000, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) RK3588_CPULCLK_RATE(1608000000, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RK3588_CPULCLK_RATE(1584000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RK3588_CPULCLK_RATE(1560000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RK3588_CPULCLK_RATE(1536000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RK3588_CPULCLK_RATE(1512000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) RK3588_CPULCLK_RATE(1488000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RK3588_CPULCLK_RATE(1464000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RK3588_CPULCLK_RATE(1440000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RK3588_CPULCLK_RATE(1416000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) RK3588_CPULCLK_RATE(1392000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) RK3588_CPULCLK_RATE(1368000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RK3588_CPULCLK_RATE(1344000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RK3588_CPULCLK_RATE(1320000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) RK3588_CPULCLK_RATE(1296000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RK3588_CPULCLK_RATE(1272000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RK3588_CPULCLK_RATE(1248000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RK3588_CPULCLK_RATE(1224000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RK3588_CPULCLK_RATE(1200000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RK3588_CPULCLK_RATE(1104000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) RK3588_CPULCLK_RATE(1008000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) RK3588_CPULCLK_RATE(912000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RK3588_CPULCLK_RATE(816000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RK3588_CPULCLK_RATE(696000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RK3588_CPULCLK_RATE(600000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RK3588_CPULCLK_RATE(408000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RK3588_CPULCLK_RATE(312000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) RK3588_CPULCLK_RATE(216000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RK3588_CPULCLK_RATE(96000000, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .div_core_shift[1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .div_core_mask[1] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .div_core_shift[2] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .div_core_mask[2] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .div_core_shift[3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .div_core_mask[3] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .mux_core_main = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mux_core_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PNAME(mux_pll_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PNAME(gpll_24m_p) = { "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PNAME(gpll_aupll_p) = { "gpll", "aupll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PNAME(gpll_lpll_p) = { "gpll", "lpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PNAME(gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PNAME(gpll_spll_p) = { "gpll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PNAME(mux_400m_200m_100m_24m_p) = {"clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RK3588_CLKSEL_CON(26), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RK3588_CLKSEL_CON(28), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) RK3588_CLKSEL_CON(30), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RK3588_CLKSEL_CON(32), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) RK3588_CLKSEL_CON(120), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RK3588_CLKSEL_CON(142), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RK3588_CLKSEL_CON(146), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RK3588_CLKSEL_CON(148), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RK3588_CLKSEL_CON(131), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RK3588_CLKSEL_CON(122), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) RK3588_CLKSEL_CON(155), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3588_CLKSEL_CON(157), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RK3588_CLKSEL_CON(34), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) RK3588_CLKSEL_CON(36), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RK3588_CLKSEL_CON(124), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RK3588_CLKSEL_CON(150), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RK3588_CLKSEL_CON(152), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RK3588_CLKSEL_CON(126), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) RK3588_CLKSEL_CON(43), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RK3588_CLKSEL_CON(45), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) RK3588_CLKSEL_CON(47), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RK3588_CLKSEL_CON(49), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) RK3588_CLKSEL_CON(51), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RK3588_CLKSEL_CON(53), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RK3588_CLKSEL_CON(55), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RK3588_CLKSEL_CON(57), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RK3588_CLKSEL_CON(59), 0, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) RK3588_CLKSEL_CON(140), 0, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0, RK3588_PLL_CON(88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 0, RK3588_PLL_CON(96),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CLK_IGNORE_UNUSED, RK3588_PLL_CON(104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) CLK_IGNORE_UNUSED, RK3588_PLL_CON(112),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 0, RK3588_PLL_CON(120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * CRU Clock-Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RK3588_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK3588_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RK3588_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RK3588_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RK3588_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RK3588_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RK3588_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RK3588_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RK3588_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RK3588_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RK3588_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RK3588_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RK3588_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK3588_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK3588_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RK3588_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RK3588_CLKSEL_CON(9), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RK3588_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RK3588_CLKSEL_CON(9), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RK3588_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RK3588_CLKSEL_CON(9), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RK3588_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RK3588_CLKSEL_CON(9), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RK3588_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RK3588_CLKSEL_CON(9), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RK3588_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) RK3588_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RK3588_CLKSEL_CON(8), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RK3588_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RK3588_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RK3588_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RK3588_CLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RK3588_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RK3588_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RK3588_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) RK3588_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RK3588_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) RK3588_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RK3588_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RK3588_CLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) RK3588_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) RK3588_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RK3588_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RK3588_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* bigcore0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* bigcore1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* dsu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) RK3588_CLKSEL_CON(24), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RK3588_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RK3588_CLKSEL_CON(24), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RK3588_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) RK3588_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) RK3588_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RK3588_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RK3588_CLKSEL_CON(29), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) RK3588_CLKGATE_CON(7), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &rk3588_i2s2_2ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RK3588_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RK3588_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RK3588_CLKSEL_CON(31), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RK3588_CLKGATE_CON(8), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &rk3588_i2s3_2ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) RK3588_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) RK3588_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) RK3588_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) RK3588_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RK3588_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RK3588_CLKSEL_CON(25), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) RK3588_CLKGATE_CON(7), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &rk3588_i2s0_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RK3588_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) RK3588_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) RK3588_CLKSEL_CON(27), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) RK3588_CLKGATE_CON(7), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &rk3588_i2s0_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) RK3588_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RK3588_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RK3588_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) RK3588_CLKGATE_CON(8), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) RK3588_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) RK3588_CLKSEL_CON(33), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) RK3588_CLKGATE_CON(9), 0, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &rk3588_spdif0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) RK3588_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK3588_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RK3588_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RK3588_CLKSEL_CON(35), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) RK3588_CLKGATE_CON(9), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &rk3588_spdif1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RK3588_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RK3588_CLKGATE_CON(68), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RK3588_CLKSEL_CON(163), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) RK3588_CLKGATE_CON(68), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) RK3588_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) RK3588_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK3588_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RK3588_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RK3588_CLKGATE_CON(19), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RK3588_CLKGATE_CON(19), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) RK3588_CLKGATE_CON(19), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) RK3588_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RK3588_CLKSEL_CON(59), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) RK3588_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RK3588_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) RK3588_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) RK3588_CLKSEL_CON(59), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RK3588_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RK3588_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RK3588_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RK3588_CLKSEL_CON(60), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RK3588_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RK3588_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RK3588_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RK3588_CLKGATE_CON(15), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK3588_CLKSEL_CON(60), 2, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) RK3588_CLKGATE_CON(15), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) RK3588_CLKGATE_CON(15), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) RK3588_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RK3588_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK3588_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) RK3588_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RK3588_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) RK3588_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RK3588_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) RK3588_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RK3588_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RK3588_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) RK3588_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) RK3588_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) RK3588_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) RK3588_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) RK3588_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) RK3588_CLKGATE_CON(11), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) RK3588_CLKGATE_CON(11), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) RK3588_CLKGATE_CON(11), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) RK3588_CLKGATE_CON(11), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) RK3588_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) RK3588_CLKGATE_CON(17), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) RK3588_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) RK3588_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) RK3588_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) RK3588_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) RK3588_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RK3588_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) RK3588_CLKGATE_CON(16), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) RK3588_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) RK3588_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) RK3588_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) RK3588_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) RK3588_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) RK3588_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) RK3588_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) RK3588_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) RK3588_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) RK3588_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) RK3588_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) RK3588_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) RK3588_CLKGATE_CON(10), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) RK3588_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) RK3588_CLKSEL_CON(38), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) RK3588_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) RK3588_CLKSEL_CON(38), 7, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RK3588_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) RK3588_CLKSEL_CON(38), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) RK3588_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) RK3588_CLKSEL_CON(38), 9, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) RK3588_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RK3588_CLKSEL_CON(38), 10, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) RK3588_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) RK3588_CLKSEL_CON(38), 11, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) RK3588_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) RK3588_CLKSEL_CON(38), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) RK3588_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) RK3588_CLKSEL_CON(38), 13, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) RK3588_CLKGATE_CON(11), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RK3588_CLKGATE_CON(18), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) RK3588_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) RK3588_CLKGATE_CON(18), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) RK3588_CLKGATE_CON(18), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) RK3588_CLKGATE_CON(18), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) RK3588_CLKGATE_CON(11), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) RK3588_CLKGATE_CON(11), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) RK3588_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) RK3588_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) RK3588_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) RK3588_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) RK3588_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) RK3588_CLKSEL_CON(59), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) RK3588_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RK3588_CLKSEL_CON(59), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) RK3588_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) RK3588_CLKSEL_CON(59), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) RK3588_CLKGATE_CON(14), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) RK3588_CLKSEL_CON(59), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) RK3588_CLKGATE_CON(14), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) RK3588_CLKSEL_CON(59), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) RK3588_CLKGATE_CON(14), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) RK3588_CLKGATE_CON(18), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) RK3588_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) RK3588_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RK3588_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) RK3588_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) RK3588_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) RK3588_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) RK3588_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) RK3588_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) RK3588_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) RK3588_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RK3588_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) RK3588_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) RK3588_CLKSEL_CON(42), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RK3588_CLKGATE_CON(12), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) &rk3588_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) RK3588_CLKGATE_CON(12), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) RK3588_CLKGATE_CON(12), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) RK3588_CLKSEL_CON(44), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) RK3588_CLKGATE_CON(12), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) &rk3588_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) RK3588_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) RK3588_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) RK3588_CLKSEL_CON(46), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) RK3588_CLKGATE_CON(13), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) &rk3588_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) RK3588_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) RK3588_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) RK3588_CLKSEL_CON(48), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) RK3588_CLKGATE_CON(13), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) &rk3588_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) RK3588_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) RK3588_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) RK3588_CLKSEL_CON(50), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) RK3588_CLKGATE_CON(13), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) &rk3588_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) RK3588_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) RK3588_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) RK3588_CLKSEL_CON(52), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) RK3588_CLKGATE_CON(13), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) &rk3588_uart6_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) RK3588_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) RK3588_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) RK3588_CLKSEL_CON(54), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) RK3588_CLKGATE_CON(13), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) &rk3588_uart7_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) RK3588_CLKGATE_CON(13), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) RK3588_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) RK3588_CLKSEL_CON(56), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) RK3588_CLKGATE_CON(14), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &rk3588_uart8_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) RK3588_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) RK3588_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) RK3588_CLKSEL_CON(58), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) RK3588_CLKGATE_CON(14), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) &rk3588_uart9_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RK3588_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) RK3588_CLKSEL_CON(165), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) RK3588_CLKGATE_CON(69), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) RK3588_CLKSEL_CON(165), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) RK3588_CLKGATE_CON(69), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) RK3588_CLKSEL_CON(165), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) RK3588_CLKGATE_CON(69), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) RK3588_CLKGATE_CON(69), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) RK3588_CLKGATE_CON(69), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) RK3588_CLKGATE_CON(69), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) RK3588_CLKSEL_CON(165), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) RK3588_CLKGATE_CON(69), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) RK3588_CLKSEL_CON(165), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) RK3588_CLKGATE_CON(69), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) RK3588_CLKGATE_CON(69), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) RK3588_CLKSEL_CON(165), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) RK3588_CLKGATE_CON(69), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) RK3588_CLKGATE_CON(70), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) RK3588_CLKGATE_CON(70), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) RK3588_CLKGATE_CON(70), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) RK3588_CLKGATE_CON(70), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) RK3588_CLKGATE_CON(70), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) RK3588_CLKGATE_CON(70), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) RK3588_CLKGATE_CON(70), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) RK3588_CLKGATE_CON(70), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* gpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) RK3588_CLKGATE_CON(66), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RK3588_CLKGATE_CON(66), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) RK3588_CLKGATE_CON(66), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) RK3588_CLKSEL_CON(159), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) RK3588_CLKGATE_CON(66), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) RK3588_CLKGATE_CON(67), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) RK3588_CLKGATE_CON(67), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* isp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) RK3588_CLKGATE_CON(26), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) RK3588_CLKSEL_CON(67), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) RK3588_CLKGATE_CON(26), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) RK3588_CLKGATE_CON(26), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) RK3588_CLKGATE_CON(26), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) RK3588_CLKGATE_CON(26), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* npu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) RK3588_CLKSEL_CON(73), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) RK3588_CLKGATE_CON(29), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) RK3588_CLKGATE_CON(29), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) RK3588_CLKSEL_CON(74), 1, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) RK3588_CLKGATE_CON(29), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) RK3588_CLKGATE_CON(27), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) RK3588_CLKGATE_CON(27), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) RK3588_CLKGATE_CON(28), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) RK3588_CLKGATE_CON(28), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RK3588_CLKSEL_CON(74), 5, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) RK3588_CLKGATE_CON(30), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) RK3588_CLKGATE_CON(30), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) RK3588_CLKGATE_CON(30), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) RK3588_CLKGATE_CON(29), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) RK3588_CLKGATE_CON(29), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) RK3588_CLKGATE_CON(29), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) RK3588_CLKGATE_CON(29), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) RK3588_CLKGATE_CON(30), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) RK3588_CLKGATE_CON(30), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) RK3588_CLKGATE_CON(29), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) RK3588_CLKSEL_CON(74), 3, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RK3588_CLKGATE_CON(29), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) RK3588_CLKGATE_CON(29), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) RK3588_CLKGATE_CON(29), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) RK3588_CLKGATE_CON(29), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) RK3588_CLKGATE_CON(29), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* nvm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) RK3588_CLKGATE_CON(31), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) RK3588_CLKGATE_CON(31), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) RK3588_CLKGATE_CON(31), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) RK3588_CLKGATE_CON(31), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) RK3588_CLKGATE_CON(31), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) RK3588_CLKGATE_CON(31), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) RK3588_CLKGATE_CON(31), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* php */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) RK3588_CLKGATE_CON(34), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) RK3588_CLKGATE_CON(34), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RK3588_CLKGATE_CON(35), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) RK3588_CLKGATE_CON(35), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) RK3588_CLKGATE_CON(32), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) RK3588_CLKGATE_CON(32), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) RK3588_CLKSEL_CON(80), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) RK3588_CLKGATE_CON(32), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) RK3588_CLKGATE_CON(34), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) RK3588_CLKGATE_CON(32), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) RK3588_CLKGATE_CON(34), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) RK3588_CLKGATE_CON(34), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) RK3588_CLKGATE_CON(32), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) RK3588_CLKGATE_CON(32), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) RK3588_CLKGATE_CON(32), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) RK3588_CLKGATE_CON(33), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) RK3588_CLKGATE_CON(33), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) RK3588_CLKGATE_CON(33), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) RK3588_CLKGATE_CON(33), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) RK3588_CLKGATE_CON(33), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) RK3588_CLKGATE_CON(33), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) RK3588_CLKGATE_CON(33), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) RK3588_CLKGATE_CON(33), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) RK3588_CLKGATE_CON(33), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) RK3588_CLKGATE_CON(33), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) RK3588_CLKGATE_CON(33), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) RK3588_CLKGATE_CON(33), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) RK3588_CLKGATE_CON(33), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) RK3588_CLKGATE_CON(33), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) RK3588_CLKGATE_CON(33), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) RK3588_CLKGATE_CON(33), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) RK3588_CLKGATE_CON(34), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) RK3588_CLKGATE_CON(34), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) RK3588_CLKGATE_CON(34), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) RK3588_CLKGATE_CON(34), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) RK3588_CLKGATE_CON(34), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) RK3588_CLKGATE_CON(34), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) RK3588_CLKGATE_CON(37), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) RK3588_CLKGATE_CON(37), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) RK3588_CLKGATE_CON(37), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) RK3588_CLKGATE_CON(32), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) RK3588_CLKGATE_CON(32), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) RK3588_CLKGATE_CON(32), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) RK3588_CLKGATE_CON(32), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) RK3588_CLKGATE_CON(37), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) RK3588_CLKGATE_CON(37), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) RK3588_CLKGATE_CON(37), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) RK3588_CLKGATE_CON(37), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) RK3588_CLKGATE_CON(37), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) RK3588_CLKGATE_CON(37), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) RK3588_CLKGATE_CON(37), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) RK3588_CLKGATE_CON(37), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) RK3588_CLKGATE_CON(37), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) RK3588_CLKGATE_CON(35), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) RK3588_CLKGATE_CON(35), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) RK3588_CLKGATE_CON(35), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) RK3588_CLKGATE_CON(35), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* rga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) RK3588_CLKGATE_CON(76), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) RK3588_CLKGATE_CON(76), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) RK3588_CLKSEL_CON(174), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) RK3588_CLKGATE_CON(76), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) RK3588_CLKGATE_CON(76), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) RK3588_CLKGATE_CON(76), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* vdec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) RK3588_CLKSEL_CON(89), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) RK3588_CLKGATE_CON(40), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) RK3588_CLKGATE_CON(40), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) RK3588_CLKGATE_CON(40), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) RK3588_CLKGATE_CON(40), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) RK3588_CLKGATE_CON(40), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) RK3588_CLKGATE_CON(40), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) RK3588_CLKSEL_CON(93), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) RK3588_CLKGATE_CON(41), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) RK3588_CLKGATE_CON(41), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) RK3588_CLKGATE_CON(41), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) RK3588_CLKGATE_CON(41), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) RK3588_CLKGATE_CON(41), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* sdio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) RK3588_CLKSEL_CON(172), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) RK3588_CLKGATE_CON(75), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) RK3588_CLKGATE_CON(75), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* usb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) RK3588_CLKGATE_CON(42), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) RK3588_CLKSEL_CON(96), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) RK3588_CLKGATE_CON(42), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) RK3588_CLKGATE_CON(42), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) RK3588_CLKGATE_CON(42), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) RK3588_CLKGATE_CON(42), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) RK3588_CLKGATE_CON(42), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* vdpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) RK3588_CLKGATE_CON(44), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) RK3588_CLKGATE_CON(44), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) RK3588_CLKGATE_CON(44), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) RK3588_CLKGATE_CON(44), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) RK3588_CLKGATE_CON(45), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) RK3588_CLKGATE_CON(45), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) RK3588_CLKGATE_CON(44), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) RK3588_CLKGATE_CON(44), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) RK3588_CLKGATE_CON(44), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) RK3588_CLKGATE_CON(45), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) RK3588_CLKGATE_CON(45), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) RK3588_CLKGATE_CON(45), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) RK3588_CLKGATE_CON(45), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) RK3588_CLKGATE_CON(45), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) RK3588_CLKGATE_CON(45), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) RK3588_CLKGATE_CON(45), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) RK3588_CLKGATE_CON(45), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) RK3588_CLKGATE_CON(44), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* venc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) RK3588_CLKSEL_CON(104), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) RK3588_CLKGATE_CON(48), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) RK3588_CLKGATE_CON(48), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) RK3588_CLKSEL_CON(102), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) RK3588_CLKGATE_CON(47), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) RK3588_CLKGATE_CON(47), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) RK3588_CLKGATE_CON(47), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) RK3588_CLKGATE_CON(47), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) RK3588_CLKGATE_CON(47), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) RK3588_CLKGATE_CON(48), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* vi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) RK3588_CLKGATE_CON(49), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) RK3588_CLKGATE_CON(49), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) RK3588_CLKSEL_CON(106), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) RK3588_CLKGATE_CON(49), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) RK3588_CLKSEL_CON(108), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) RK3588_CLKGATE_CON(51), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) RK3588_CLKGATE_CON(51), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) RK3588_CLKGATE_CON(51), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) RK3588_CLKGATE_CON(50), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RK3588_CLKGATE_CON(50), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) RK3588_CLKGATE_CON(50), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) RK3588_CLKGATE_CON(50), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) RK3588_CLKGATE_CON(50), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) RK3588_CLKGATE_CON(50), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) RK3588_CLKGATE_CON(49), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) RK3588_CLKGATE_CON(49), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) RK3588_CLKGATE_CON(50), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) RK3588_CLKGATE_CON(50), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) RK3588_CLKGATE_CON(50), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) RK3588_CLKGATE_CON(50), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) RK3588_CLKGATE_CON(49), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) RK3588_CLKGATE_CON(49), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) RK3588_CLKGATE_CON(49), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) RK3588_CLKGATE_CON(49), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) RK3588_CLKGATE_CON(49), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) RK3588_CLKGATE_CON(49), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) RK3588_CLKGATE_CON(49), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) RK3588_CLKGATE_CON(49), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* vo0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) RK3588_CLKGATE_CON(55), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) RK3588_CLKSEL_CON(116), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) RK3588_CLKGATE_CON(55), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) RK3588_CLKSEL_CON(116), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) RK3588_CLKGATE_CON(55), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RK3588_CLKSEL_CON(116), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) RK3588_CLKGATE_CON(55), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RK3588_CLKSEL_CON(116), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) RK3588_CLKGATE_CON(55), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) RK3588_CLKGATE_CON(56), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) RK3588_CLKGATE_CON(56), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) RK3588_CLKGATE_CON(56), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) RK3588_CLKGATE_CON(56), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) RK3588_CLKGATE_CON(56), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) RK3588_CLKGATE_CON(56), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) RK3588_CLKGATE_CON(55), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) RK3588_CLKGATE_CON(55), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) RK3588_CLKGATE_CON(56), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) RK3588_CLKGATE_CON(56), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) RK3588_CLKGATE_CON(55), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) RK3588_CLKGATE_CON(56), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) RK3588_CLKSEL_CON(119), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) RK3588_CLKGATE_CON(56), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) &rk3588_i2s4_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RK3588_CLKGATE_CON(56), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) RK3588_CLKGATE_CON(56), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) RK3588_CLKSEL_CON(121), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) RK3588_CLKGATE_CON(57), 0, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) &rk3588_i2s8_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) RK3588_CLKGATE_CON(57), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) RK3588_CLKGATE_CON(57), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) RK3588_CLKSEL_CON(123), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) RK3588_CLKGATE_CON(57), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) &rk3588_spdif2_dp0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) RK3588_CLKGATE_CON(57), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) RK3588_CLKGATE_CON(57), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) RK3588_CLKGATE_CON(57), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) RK3588_CLKSEL_CON(125), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) RK3588_CLKGATE_CON(57), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) &rk3588_spdif5_dp1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) RK3588_CLKGATE_CON(57), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) RK3588_CLKGATE_CON(57), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) RK3588_CLKSEL_CON(117), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) RK3588_CLKGATE_CON(56), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) RK3588_CLKSEL_CON(117), 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) RK3588_CLKGATE_CON(56), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* vo1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) RK3588_CLKGATE_CON(65), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) RK3588_CLKGATE_CON(59), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) RK3588_CLKGATE_CON(59), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) RK3588_CLKSEL_CON(128), 13, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) RK3588_CLKGATE_CON(59), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) RK3588_CLKSEL_CON(129), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) RK3588_CLKGATE_CON(59), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) RK3588_CLKSEL_CON(129), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) RK3588_CLKGATE_CON(59), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) RK3588_CLKSEL_CON(129), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RK3588_CLKGATE_CON(59), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) RK3588_CLKGATE_CON(52), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) FACTOR(ACLK_VOP_DIV2_SRC, "aclk_vop_div2_src", "aclk_vop_root", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) RK3588_CLKGATE_CON(52), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) RK3588_CLKGATE_CON(52), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) RK3588_CLKSEL_CON(110), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) RK3588_CLKGATE_CON(52), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) RK3588_CLKGATE_CON(74), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) RK3588_CLKSEL_CON(170), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) RK3588_CLKGATE_CON(74), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) COMPOSITE_NODIV(ACLK_VOP, "aclk_vop", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) RK3588_CLKSEL_CON(115), 9, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) RK3588_CLKGATE_CON(52), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) RK3588_CLKGATE_CON(62), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) RK3588_CLKGATE_CON(62), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) RK3588_CLKSEL_CON(140), 1, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RK3588_CLKGATE_CON(62), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) RK3588_CLKGATE_CON(62), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) RK3588_CLKGATE_CON(62), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) RK3588_CLKSEL_CON(140), 3, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) RK3588_CLKGATE_CON(62), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) RK3588_CLKGATE_CON(60), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) RK3588_CLKGATE_CON(60), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) RK3588_CLKGATE_CON(61), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) RK3588_CLKGATE_CON(61), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) RK3588_CLKGATE_CON(61), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) RK3588_CLKGATE_CON(61), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) RK3588_CLKSEL_CON(139), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) RK3588_CLKGATE_CON(61), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) &rk3588_hdmirx_aud_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) RK3588_CLKGATE_CON(61), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) RK3588_CLKGATE_CON(60), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) RK3588_CLKGATE_CON(60), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) RK3588_CLKGATE_CON(61), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) RK3588_CLKGATE_CON(61), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) RK3588_CLKGATE_CON(61), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) RK3588_CLKGATE_CON(61), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) RK3588_CLKGATE_CON(60), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) RK3588_CLKGATE_CON(60), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) RK3588_CLKGATE_CON(59), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) RK3588_CLKGATE_CON(59), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) RK3588_CLKGATE_CON(59), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) RK3588_CLKGATE_CON(65), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) RK3588_CLKGATE_CON(65), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) RK3588_CLKSEL_CON(156), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) RK3588_CLKGATE_CON(65), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) &rk3588_i2s10_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) RK3588_CLKGATE_CON(65), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) RK3588_CLKGATE_CON(60), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) RK3588_CLKSEL_CON(130), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) RK3588_CLKGATE_CON(60), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) &rk3588_i2s7_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) RK3588_CLKGATE_CON(60), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) RK3588_CLKGATE_CON(65), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) RK3588_CLKSEL_CON(154), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) RK3588_CLKGATE_CON(65), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) &rk3588_i2s9_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) RK3588_CLKGATE_CON(65), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) RK3588_CLKGATE_CON(62), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) RK3588_CLKSEL_CON(141), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) RK3588_CLKGATE_CON(62), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) &rk3588_i2s5_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) RK3588_CLKGATE_CON(62), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RK3588_CLKGATE_CON(62), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) RK3588_CLKSEL_CON(145), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) RK3588_CLKGATE_CON(62), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) &rk3588_i2s6_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) RK3588_CLKGATE_CON(62), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) RK3588_CLKGATE_CON(63), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) RK3588_CLKSEL_CON(147), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) RK3588_CLKGATE_CON(63), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) &rk3588_i2s6_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) RK3588_CLKGATE_CON(63), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) RK3588_CLKSEL_CON(148), 2, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) RK3588_CLKGATE_CON(63), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) RK3588_CLKSEL_CON(149), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) RK3588_CLKGATE_CON(63), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) &rk3588_spdif3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) RK3588_CLKGATE_CON(63), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) RK3588_CLKGATE_CON(63), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) RK3588_CLKSEL_CON(151), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) RK3588_CLKGATE_CON(63), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) &rk3588_spdif4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) RK3588_CLKGATE_CON(63), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) RK3588_CLKGATE_CON(63), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) RK3588_CLKGATE_CON(63), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) RK3588_CLKGATE_CON(64), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) RK3588_CLKGATE_CON(73), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) RK3588_CLKGATE_CON(73), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) RK3588_CLKGATE_CON(72), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) RK3588_CLKGATE_CON(72), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) RK3588_CLKGATE_CON(72), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) RK3588_CLKGATE_CON(72), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) RK3588_CLKGATE_CON(52), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) RK3588_CLKGATE_CON(52), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) RK3588_CLKGATE_CON(52), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) RK3588_CLKGATE_CON(52), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) RK3588_CLKSEL_CON(112), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) RK3588_CLKGATE_CON(52), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) RK3588_CLKSEL_CON(112), 9, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) RK3588_CLKGATE_CON(53), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) RK3588_CLKSEL_CON(112), 11, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) RK3588_CLKGATE_CON(53), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) RK3588_CLKGATE_CON(53), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) RK3588_CLKGATE_CON(53), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) RK3588_CLKGATE_CON(53), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) RK3588_CLKGATE_CON(53), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) RK3588_CLKGATE_CON(53), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) RK3588_CLKGATE_CON(53), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) RK3588_CLKGATE_CON(53), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) RK3588_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) RK3588_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) RK3588_CLKGATE_CON(77), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) RK3588_CLKGATE_CON(77), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) RK3588_CLKGATE_CON(77), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) RK3588_CLKSEL_CON(176), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) RK3588_CLKGATE_CON(77), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) RK3588_CLKSEL_CON(176), 6, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) RK3588_CLKGATE_CON(77), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) RK3588_CLKSEL_CON(177), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) RK3588_CLKGATE_CON(77), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) RK3588_CLKSEL_CON(177), 6, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) RK3588_CLKSEL_CON(177), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) RK3588_CLKSEL_CON(177), 8, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* pmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) RK3588_PMU_CLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) &rk3588_i2s1_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) RK3588_PMU_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) &rk3588_i2s1_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) RK3588_PMU_CLKSEL_CON(4), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) &rk3588_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) RK3588_CLKGATE_CON(63), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) RK3588_CLKGATE_CON(63), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) RK3588_CLKGATE_CON(64), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) RK3588_CLKGATE_CON(63), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) RK3588_CLKGATE_CON(63), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) RK3588_CLKGATE_CON(63), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) RK3588_CLKGATE_CON(62), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) RK3588_CLKGATE_CON(65), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) RK3588_CLKGATE_CON(60), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) RK3588_CLKGATE_CON(65), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) RK3588_CLKGATE_CON(60), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) RK3588_CLKGATE_CON(60), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) RK3588_CLKGATE_CON(57), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) RK3588_CLKGATE_CON(57), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) RK3588_CLKGATE_CON(56), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) RK3588_CLKGATE_CON(56), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) RK3588_CLKGATE_CON(55), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) RK3588_CLKGATE_CON(55), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) RK3588_CLKGATE_CON(48), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) RK3588_CLKGATE_CON(48), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) RK3588_CLKGATE_CON(44), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) RK3588_CLKGATE_CON(45), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) RK3588_CLKGATE_CON(44), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) RK3588_CLKGATE_CON(44), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) RK3588_CLKGATE_CON(44), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) RK3588_CLKGATE_CON(45), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) RK3588_CLKGATE_CON(45), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) RK3588_CLKGATE_CON(42), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) RK3588_CLKGATE_CON(42), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) RK3588_CLKGATE_CON(42), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) RK3588_CLKGATE_CON(42), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) RK3588_CLKGATE_CON(42), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) RK3588_CLKGATE_CON(42), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) RK3588_CLKGATE_CON(75), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) RK3588_CLKGATE_CON(41), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) RK3588_CLKGATE_CON(41), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) RK3588_CLKGATE_CON(40), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) RK3588_CLKGATE_CON(40), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) RK3588_CLKGATE_CON(39), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) RK3588_CLKGATE_CON(39), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) RK3588_CLKGATE_CON(38), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) RK3588_CLKGATE_CON(38), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) RK3588_CLKGATE_CON(38), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) RK3588_CLKGATE_CON(38), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) RK3588_CLKGATE_CON(38), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) RK3588_CLKGATE_CON(38), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) RK3588_CLKGATE_CON(38), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) RK3588_CLKGATE_CON(38), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) RK3588_CLKGATE_CON(38), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) RK3588_CLKGATE_CON(38), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) RK3588_CLKGATE_CON(31), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) RK3588_CLKGATE_CON(31), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) RK3588_CLKGATE_CON(31), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) RK3588_CLKGATE_CON(26), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) RK3588_CLKGATE_CON(26), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) RK3588_CLKGATE_CON(68), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) RK3588_CLKGATE_CON(68), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static void __iomem *rk3588_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static void rk3588_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (rk3588_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) pr_warn("DSU CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) 32, 4, rk3588_cru_base + RK3588_DSU_CRU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) 0x330, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) pr_warn("BIGCORE0 CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) 32, 4, rk3588_cru_base + RK3588_BIGCORE0_CRU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) 0x300, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) pr_warn("BIGCORE1 CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) 32, 4, rk3588_cru_base + RK3588_BIGCORE1_CRU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) 0x300, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static void __init rk3588_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) rk3588_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) rockchip_clk_register_plls(ctx, rk3588_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ARRAY_SIZE(rk3588_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) RK3588_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) 3, clks[PLL_LPLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) &rk3588_cpulclk_data, rk3588_cpulclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ARRAY_SIZE(rk3588_cpulclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) 3, clks[PLL_B0PLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) &rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ARRAY_SIZE(rk3588_cpub0clk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) 3, clks[PLL_B1PLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) &rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) ARRAY_SIZE(rk3588_cpub1clk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) rockchip_clk_register_branches(ctx, rk3588_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ARRAY_SIZE(rk3588_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) rockchip_register_softrst(np, 49158, reg_base + RK3588_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (!rk_dump_cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) rk_dump_cru = rk3588_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) struct clk_rk3588_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static const struct clk_rk3588_inits clk_3588_cru_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .inits = rk3588_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const struct of_device_id clk_rk3588_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .compatible = "rockchip,rk3588-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .data = &clk_3588_cru_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) MODULE_DEVICE_TABLE(of, clk_rk3588_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static int __init clk_rk3588_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) const struct clk_rk3588_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) match = of_match_device(clk_rk3588_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static struct platform_driver clk_rk3588_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .name = "clk-rk3588",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .of_match_table = clk_rk3588_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) MODULE_DESCRIPTION("Rockchip RK3588 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags