^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/rk3568-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3568_GRF_SOC_CON1 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3568_GRF_SOC_CON2 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3568_GRF_SOC_STATUS0 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3568_PMU_GRF_SOC_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RK3568_FRAC_MAX_PRATE 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RK3568_SPDIF_FRAC_MAX_PRATE 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK3568_UART_FRAC_MAX_PRATE 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RK3568_DCLK_PARENT_MAX_PRATE 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum rk3568_pmu_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ppll, hpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum rk3568_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) apll, dpll, gpll, cpll, npll, vpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RK3568_DIV_ATCLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK3568_DIV_ATCLK_CORE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RK3568_DIV_GICCLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RK3568_DIV_GICCLK_CORE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RK3568_DIV_PCLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RK3568_DIV_PCLK_CORE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RK3568_DIV_ACLK_CORE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RK3568_DIV_ACLK_CORE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RK3568_DIV_SCLK_CORE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RK3568_DIV_SCLK_CORE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RK3568_MUX_SCLK_CORE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RK3568_MUX_SCLK_CORE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RK3568_MUX_CLK_CORE_APLL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RK3568_MUX_CLK_CORE_APLL_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RK3568_MUX_CLK_PVTPLL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RK3568_MUX_CLK_PVTPLL_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RK3568_CLKSEL1(_sclk_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .reg = RK3568_CLKSEL_CON(2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RK3568_MUX_SCLK_CORE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RK3568_DIV_SCLK_CORE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RK3568_CLKSEL2(_aclk_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .reg = RK3568_CLKSEL_CON(5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RK3568_DIV_ACLK_CORE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RK3568_CLKSEL3(_atclk_core, _gic_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .reg = RK3568_CLKSEL_CON(3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RK3568_DIV_ATCLK_CORE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) RK3568_DIV_GICCLK_CORE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RK3568_CLKSEL4(_pclk_core, _periph_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .reg = RK3568_CLKSEL_CON(4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RK3568_DIV_PCLK_CORE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) RK3568_CLKSEL1(_sclk), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RK3568_CLKSEL2(_acore), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RK3568_CLKSEL3(_atcore, _gicclk), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RK3568_CLKSEL4(_pclk, _periph), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .core_reg[0] = RK3568_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .core_reg[1] = RK3568_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .div_core_shift[1] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .div_core_mask[1] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .core_reg[2] = RK3568_CLKSEL_CON(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .div_core_shift[2] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .div_core_mask[2] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .core_reg[3] = RK3568_CLKSEL_CON(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .div_core_shift[3] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .div_core_mask[3] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .num_cores = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_pll_p) = { "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PNAME(npll_gpll_p) = { "npll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PNAME(cpll_gpll_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PNAME(gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PNAME(i2s0_mclkout_tx_p) = { "mclk_i2s0_8ch_tx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PNAME(i2s0_mclkout_rx_p) = { "mclk_i2s0_8ch_rx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PNAME(i2s1_mclkout_tx_p) = { "mclk_i2s1_8ch_tx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PNAME(i2s1_mclkout_rx_p) = { "mclk_i2s1_8ch_rx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PNAME(i2s2_mclkout_p) = { "mclk_i2s2_2ch", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PNAME(i2s3_mclkout_tx_p) = { "mclk_i2s3_2ch_tx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PNAME(i2s3_mclkout_rx_p) = { "mclk_i2s3_2ch_rx", "xin_osc0_half" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PNAME(clk_32k_ioe_p) = { "clk_rtc_32k", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PNAME(i2s1_mclkout_p) = { "i2s1_mclkout_rx", "i2s1_mclkout_tx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PNAME(i2s3_mclkout_p) = { "i2s3_mclkout_rx", "i2s3_mclkout_tx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PNAME(i2s1_mclk_rx_ioe_p) = { "i2s1_mclkin_rx", "i2s1_mclkout_rx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PNAME(i2s1_mclk_tx_ioe_p) = { "i2s1_mclkin_tx", "i2s1_mclkout_tx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PNAME(i2s2_mclk_ioe_p) = { "i2s2_mclkin", "i2s2_mclkout" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PNAME(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0, RK3568_PMU_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0, RK3568_PMU_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0, RK3568_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0, RK3568_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK3568_MODE_CON0, 2, 1, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0, RK3568_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0, RK3568_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_IS_CRITICAL, RK3568_PLL_CON(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0, RK3568_PLL_CON(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* SRC_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RK3568_CLKGATE_CON(35), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RK3568_CLKGATE_CON(35), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RK3568_CLKGATE_CON(35), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RK3568_CLKGATE_CON(35), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RK3568_CLKGATE_CON(35), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RK3568_CLKGATE_CON(35), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RK3568_CLKGATE_CON(35), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RK3568_CLKGATE_CON(35), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RK3568_CLKGATE_CON(35), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RK3568_CLKGATE_CON(35), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) RK3568_CLKGATE_CON(35), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RK3568_CLKGATE_CON(35), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RK3568_CLKGATE_CON(35), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RK3568_CLKGATE_CON(35), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RK3568_CLKGATE_CON(35), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RK3568_CLKGATE_CON(35), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RK3568_MODE_CON0, 14, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RK3568_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RK3568_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) RK3568_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RK3568_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RK3568_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RK3568_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RK3568_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RK3568_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) RK3568_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RK3568_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RK3568_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RK3568_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RK3568_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) RK3568_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* PD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RK3568_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RK3568_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) RK3568_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RK3568_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RK3568_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) RK3568_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* PD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) RK3568_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", npll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) RK3568_CLKSEL_CON(7), 7, 1, MFLAGS, 4, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) RK3568_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RK3568_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) RK3568_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RK3568_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3568_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RK3568_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) RK3568_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RK3568_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) RK3568_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RK3568_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RK3568_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) RK3568_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RK3568_CLKGATE_CON(4), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* PD_GIC_AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) RK3568_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) RK3568_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RK3568_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RK3568_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) RK3568_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RK3568_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) RK3568_CLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RK3568_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RK3568_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) RK3568_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RK3568_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) RK3568_CLKSEL_CON(12), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RK3568_CLKGATE_CON(6), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &rk3568_i2s0_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RK3568_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) RK3568_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) RK3568_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) RK3568_CLKSEL_CON(14), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) RK3568_CLKGATE_CON(6), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &rk3568_i2s0_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) RK3568_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) RK3568_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RK3568_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RK3568_CLKSEL_CON(16), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RK3568_CLKGATE_CON(6), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &rk3568_i2s1_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RK3568_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RK3568_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RK3568_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RK3568_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) RK3568_CLKGATE_CON(6), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &rk3568_i2s1_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RK3568_CLKGATE_CON(6), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) RK3568_CLKGATE_CON(6), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) RK3568_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RK3568_CLKSEL_CON(20), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) RK3568_CLKGATE_CON(7), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &rk3568_i2s2_2ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RK3568_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RK3568_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) RK3568_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RK3568_CLKSEL_CON(22), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RK3568_CLKGATE_CON(7), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &rk3568_i2s3_2ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RK3568_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RK3568_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RK3568_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) RK3568_CLKSEL_CON(84), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RK3568_CLKGATE_CON(7), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &rk3568_i2s3_2ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RK3568_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RK3568_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RK3568_CLKGATE_CON(5), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RK3568_CLKGATE_CON(5), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RK3568_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RK3568_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RK3568_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RK3568_CLKSEL_CON(24), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RK3568_CLKGATE_CON(7), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) &rk3568_spdif_8ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RK3568_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RK3568_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RK3568_CLKSEL_CON(26), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RK3568_CLKGATE_CON(8), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) &rk3568_audpwm_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RK3568_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RK3568_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RK3568_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RK3568_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* PD_SECURE_FLASH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RK3568_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RK3568_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) RK3568_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) RK3568_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RK3568_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) RK3568_CLKGATE_CON(8), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RK3568_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RK3568_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) RK3568_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) RK3568_CLKGATE_CON(26), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) RK3568_CLKGATE_CON(26), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) RK3568_CLKGATE_CON(26), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) RK3568_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RK3568_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) RK3568_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RK3568_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) RK3568_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) RK3568_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) RK3568_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) RK3568_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RK3568_CLKGATE_CON(9), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RK3568_CLKGATE_CON(9), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* PD_PIPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK3568_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RK3568_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) RK3568_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) RK3568_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RK3568_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) RK3568_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RK3568_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RK3568_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RK3568_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RK3568_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RK3568_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RK3568_CLKGATE_CON(12), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) RK3568_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RK3568_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) RK3568_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) RK3568_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) RK3568_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) RK3568_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) RK3568_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) RK3568_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) RK3568_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RK3568_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RK3568_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RK3568_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RK3568_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) RK3568_CLKGATE_CON(11), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) RK3568_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RK3568_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RK3568_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) RK3568_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) RK3568_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RK3568_CLKGATE_CON(10), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RK3568_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) RK3568_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* PD_PHP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) RK3568_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) RK3568_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RK3568_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RK3568_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) RK3568_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) RK3568_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) RK3568_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) RK3568_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RK3568_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RK3568_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RK3568_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RK3568_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) RK3568_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* PD_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) RK3568_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RK3568_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RK3568_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RK3568_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) RK3568_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RK3568_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) RK3568_CLKGATE_CON(16), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) RK3568_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK3568_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) RK3568_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) RK3568_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) RK3568_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RK3568_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RK3568_CLKGATE_CON(17), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) RK3568_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RK3568_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) RK3568_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RK3568_CLKGATE_CON(18), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK3568_CLKGATE_CON(18), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RK3568_CLKGATE_CON(18), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RK3568_CLKGATE_CON(18), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RK3568_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) RK3568_CLKGATE_CON(18), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RK3568_CLKGATE_CON(18), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RK3568_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) RK3568_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) RK3568_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) RK3568_CLKGATE_CON(19), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) RK3568_CLKGATE_CON(19), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) RK3568_CLKGATE_CON(19), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) RK3568_CLKGATE_CON(19), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) RK3568_CLKGATE_CON(20), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) RK3568_CLKGATE_CON(20), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) RK3568_CLKGATE_CON(20), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) RK3568_CLKGATE_CON(20), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) RK3568_CLKGATE_CON(20), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) RK3568_CLKGATE_CON(20), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) RK3568_CLKGATE_CON(20), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) RK3568_CLKGATE_CON(20), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) RK3568_CLKGATE_CON(20), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) RK3568_CLKGATE_CON(20), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) RK3568_CLKGATE_CON(21), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) RK3568_CLKGATE_CON(21), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) RK3568_CLKGATE_CON(21), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) RK3568_CLKGATE_CON(21), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) RK3568_CLKGATE_CON(21), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) RK3568_CLKGATE_CON(21), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) RK3568_CLKGATE_CON(21), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) RK3568_CLKGATE_CON(21), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) RK3568_CLKGATE_CON(21), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) RK3568_CLKGATE_CON(21), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* PD_VPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) RK3568_CLKGATE_CON(22), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) RK3568_CLKGATE_CON(22), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) RK3568_CLKGATE_CON(22), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) RK3568_CLKGATE_CON(22), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* PD_RGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RK3568_CLKGATE_CON(23), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) RK3568_CLKGATE_CON(23), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) RK3568_CLKGATE_CON(22), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RK3568_CLKGATE_CON(23), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) RK3568_CLKGATE_CON(23), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) RK3568_CLKGATE_CON(23), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) RK3568_CLKGATE_CON(23), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) RK3568_CLKGATE_CON(23), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) RK3568_CLKGATE_CON(23), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) RK3568_CLKGATE_CON(23), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) RK3568_CLKGATE_CON(23), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) RK3568_CLKGATE_CON(23), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) RK3568_CLKGATE_CON(23), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) RK3568_CLKGATE_CON(23), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) RK3568_CLKGATE_CON(22), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) RK3568_CLKGATE_CON(22), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* PD_RKVENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) RK3568_CLKGATE_CON(24), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) RK3568_CLKGATE_CON(24), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) RK3568_CLKGATE_CON(24), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) RK3568_CLKGATE_CON(24), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RK3568_CLKGATE_CON(24), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) RK3568_CLKGATE_CON(25), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) RK3568_CLKGATE_CON(25), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) RK3568_CLKGATE_CON(25), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) RK3568_CLKGATE_CON(25), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) RK3568_CLKGATE_CON(25), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) RK3568_CLKGATE_CON(25), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) RK3568_CLKGATE_CON(25), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) RK3568_CLKGATE_CON(26), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) RK3568_CLKGATE_CON(26), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) RK3568_CLKGATE_CON(26), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) RK3568_CLKGATE_CON(26), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) RK3568_CLKGATE_CON(26), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RK3568_CLKGATE_CON(26), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) RK3568_CLKGATE_CON(26), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) RK3568_CLKGATE_CON(26), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) RK3568_CLKGATE_CON(26), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) RK3568_CLKGATE_CON(26), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) RK3568_CLKGATE_CON(32), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) RK3568_CLKGATE_CON(32), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RK3568_CLKGATE_CON(32), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) RK3568_CLKGATE_CON(27), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) RK3568_CLKGATE_CON(27), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) RK3568_CLKSEL_CON(53), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) RK3568_CLKGATE_CON(27), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) &rk3568_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) RK3568_CLKGATE_CON(27), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) RK3568_CLKGATE_CON(28), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) RK3568_CLKGATE_CON(28), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) RK3568_CLKSEL_CON(55), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) RK3568_CLKGATE_CON(28), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) &rk3568_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) RK3568_CLKGATE_CON(28), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) RK3568_CLKGATE_CON(28), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) RK3568_CLKGATE_CON(28), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) RK3568_CLKSEL_CON(57), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) RK3568_CLKGATE_CON(28), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) &rk3568_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) RK3568_CLKGATE_CON(28), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) RK3568_CLKGATE_CON(28), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) RK3568_CLKGATE_CON(28), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) RK3568_CLKSEL_CON(59), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) RK3568_CLKGATE_CON(28), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) &rk3568_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) RK3568_CLKGATE_CON(28), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) RK3568_CLKGATE_CON(28), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) RK3568_CLKGATE_CON(28), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) RK3568_CLKSEL_CON(61), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) RK3568_CLKGATE_CON(28), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &rk3568_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) RK3568_CLKGATE_CON(28), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) RK3568_CLKGATE_CON(29), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) RK3568_CLKGATE_CON(29), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RK3568_CLKSEL_CON(63), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) RK3568_CLKGATE_CON(29), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &rk3568_uart6_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) RK3568_CLKGATE_CON(29), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) RK3568_CLKGATE_CON(29), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) RK3568_CLKGATE_CON(29), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) RK3568_CLKSEL_CON(65), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) RK3568_CLKGATE_CON(29), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) &rk3568_uart7_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) RK3568_CLKGATE_CON(29), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) RK3568_CLKGATE_CON(29), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) RK3568_CLKGATE_CON(29), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) RK3568_CLKSEL_CON(67), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RK3568_CLKGATE_CON(29), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) &rk3568_uart8_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) RK3568_CLKGATE_CON(29), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) RK3568_CLKGATE_CON(29), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) RK3568_CLKGATE_CON(29), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) RK3568_CLKSEL_CON(69), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) RK3568_CLKGATE_CON(29), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &rk3568_uart9_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) RK3568_CLKGATE_CON(29), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) RK3568_CLKGATE_CON(27), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) RK3568_CLKGATE_CON(27), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) RK3568_CLKGATE_CON(27), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) RK3568_CLKGATE_CON(27), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RK3568_CLKGATE_CON(27), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) RK3568_CLKGATE_CON(27), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) RK3568_CLKGATE_CON(32), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) RK3568_CLKGATE_CON(30), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) RK3568_CLKGATE_CON(30), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) RK3568_CLKGATE_CON(30), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) RK3568_CLKGATE_CON(30), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) RK3568_CLKGATE_CON(30), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) RK3568_CLKGATE_CON(30), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) RK3568_CLKGATE_CON(30), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) RK3568_CLKGATE_CON(30), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) RK3568_CLKGATE_CON(30), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) RK3568_CLKGATE_CON(30), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) RK3568_CLKGATE_CON(30), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) RK3568_CLKGATE_CON(30), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) RK3568_CLKGATE_CON(30), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) RK3568_CLKGATE_CON(30), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) RK3568_CLKGATE_CON(30), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) RK3568_CLKGATE_CON(30), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) RK3568_CLKGATE_CON(31), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) RK3568_CLKGATE_CON(31), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) RK3568_CLKGATE_CON(31), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) RK3568_CLKGATE_CON(31), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) RK3568_CLKGATE_CON(31), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) RK3568_CLKGATE_CON(31), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) RK3568_CLKGATE_CON(32), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) RK3568_CLKGATE_CON(32), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) RK3568_CLKGATE_CON(32), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RK3568_CLKGATE_CON(32), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) RK3568_CLKGATE_CON(31), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) RK3568_CLKGATE_CON(31), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) RK3568_CLKGATE_CON(31), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) RK3568_CLKGATE_CON(31), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) RK3568_CLKGATE_CON(31), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) RK3568_CLKGATE_CON(31), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) RK3568_CLKGATE_CON(31), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) RK3568_CLKGATE_CON(31), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) RK3568_CLKGATE_CON(32), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) RK3568_CLKGATE_CON(32), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) RK3568_CLKGATE_CON(32), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) RK3568_CLKGATE_CON(32), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) RK3568_CLKGATE_CON(32), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) RK3568_CLKGATE_CON(32), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) RK3568_CLKGATE_CON(32), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* PD_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) RK3568_CLKGATE_CON(33), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) RK3568_CLKGATE_CON(33), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RK3568_CLKGATE_CON(33), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) RK3568_CLKGATE_CON(33), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) RK3568_CLKGATE_CON(33), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) RK3568_CLKGATE_CON(33), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) RK3568_CLKGATE_CON(33), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) RK3568_CLKGATE_CON(33), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) RK3568_CLKGATE_CON(33), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) RK3568_CLKGATE_CON(34), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) RK3568_CLKGATE_CON(34), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) RK3568_CLKGATE_CON(34), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) RK3568_CLKGATE_CON(34), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) RK3568_CLKGATE_CON(34), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) RK3568_CLKGATE_CON(34), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) RK3568_CLKGATE_CON(34), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* PD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) RK3568_PMU_CLKSEL_CON(1), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) &rk3568_rtc32k_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) RK3568_PMU_CLKSEL_CON(5), CLK_FRAC_DIVIDER_NO_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) &rk3568_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", clk_32k_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) RK3568_PMU_GRF_SOC_CON0, 0, 1, MFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static void __iomem *rk3568_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static void __iomem *rk3568_pmucru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static void rk3568_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (rk3568_pmucru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) pr_warn("PMU CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) 32, 4, rk3568_pmucru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) 0x248, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (rk3568_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 32, 4, rk3568_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) 0x588, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static void __init rk3568_pmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pr_err("%s: could not map cru pmu region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) rk3568_pmucru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) pr_err("%s: rockchip pmu clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ARRAY_SIZE(rk3568_pmu_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) RK3568_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ARRAY_SIZE(rk3568_clk_pmu_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static void __init rk3568_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) rk3568_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) rockchip_clk_register_plls(ctx, rk3568_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ARRAY_SIZE(rk3568_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) RK3568_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) 2, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) &rk3568_cpuclk_data, rk3568_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ARRAY_SIZE(rk3568_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) rockchip_clk_register_branches(ctx, rk3568_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ARRAY_SIZE(rk3568_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (!rk_dump_cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) rk_dump_cru = rk3568_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct clk_rk3568_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .inits = rk3568_pmu_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static const struct clk_rk3568_inits clk_3568_cru_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .inits = rk3568_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const struct of_device_id clk_rk3568_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .compatible = "rockchip,rk3568-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .data = &clk_3568_cru_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .compatible = "rockchip,rk3568-pmucru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .data = &clk_rk3568_pmucru_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static int __init clk_rk3568_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) const struct clk_rk3568_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) match = of_match_device(clk_rk3568_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static struct platform_driver clk_rk3568_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .name = "clk-rk3568",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .of_match_table = clk_rk3568_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) MODULE_ALIAS("platform:clk-rk3568");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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