^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/rk3399-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum rk3399_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) lpll, bpll, dpll, cpll, gpll, npll, vpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum rk3399_pmu_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ppll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0, 4194304), /* vco = 2982000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* CRU parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PNAME(mux_pll_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "clk_ddrc_bpll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "clk_ddrc_dpll_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "clk_ddrc_gpll_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef RK3399_TWO_PLL_FOR_VOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PNAME(mux_aclk_cci_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "gpll_aclk_cci_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "npll_aclk_cci_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "dummy_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PNAME(mux_cci_trace_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "gpll_cci_trace" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_cs_p) = { "dummy_cpll", "gpll_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "npll_cs"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_aclk_perihp_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "gpll_aclk_perihp_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_pll_src_cpll_gpll_p) = { "dummy_cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PNAME(mux_pll_src_cpll_gpll_npll_p) = { "dummy_cpll", "gpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "dummy_cpll", "gpll", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_pll_src_cpll_gpll_upll_p) = { "dummy_cpll", "gpll", "upll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "dummy_cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "dummy_cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "dummy_cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "dummy_cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "clk_usbphy_480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "dummy_cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "npll", "upll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "upll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "ppll", "upll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * We hope to be able to HDMI/DP can obtain better signal quality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * therefore, we move VOP pwm and aclk clocks to other PLLs, let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * HDMI/DP phyclock can monopolize VPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "dummy_cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mux_aclk_emmc_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "gpll_aclk_emmc_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mux_aclk_perilp0_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "gpll_aclk_perilp0_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PNAME(mux_fclk_cm0s_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "gpll_fclk_cm0s_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(mux_hclk_perilp1_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "gpll_hclk_perilp1_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PNAME(mux_aclk_gmac_p) = { "dummy_cpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "gpll_aclk_gmac_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "gpll_aclk_cci_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "npll_aclk_cci_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "dummy_vpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpll_cci_trace" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "npll_cs"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "gpll_aclk_perihp_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "clk_usbphy_480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "npll", "upll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "upll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "ppll", "upll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * We hope to be able to HDMI/DP can obtain better signal quality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * therefore, we move VOP pwm and aclk clocks to other PLLs, let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * HDMI/DP phyclock can monopolize VPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "gpll_aclk_emmc_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "gpll_aclk_perilp0_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "gpll_fclk_cm0s_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "gpll_hclk_perilp1_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "gpll_aclk_gmac_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "dummy_dclk_vop0_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "dummy_dclk_vop1_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "clk_pcie_core_phy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "clk_usbphy1_480m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "clkin_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "clkin_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "clkin_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "clkin_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "clk_i2s2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PNAME(mux_uart0_p) = { "xin24m", "clk_uart0_div", "clk_uart0_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PNAME(mux_uart1_p) = { "xin24m", "clk_uart1_div", "clk_uart1_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PNAME(mux_uart2_p) = { "xin24m", "clk_uart2_div", "clk_uart2_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PNAME(mux_uart3_p) = { "xin24m", "clk_uart3_div", "clk_uart3_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* PMU CRU parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PNAME(mux_uart4_pmu_p) = { "xin24m", "clk_uart4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "clk_uart4_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static u32 uart_mux_idx[] = { 2, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) RK3399_PLL_CON(19), 8, 31, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #ifdef RK3399_TWO_PLL_FOR_VOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RK3399_PLL_CON(27), 8, 31, 0, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) RK3399_PLL_CON(35), 8, 31, 0, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RK3399_PLL_CON(51), 8, 31, 0, rk3399_vpll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MUXTBL(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MUXTBL(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MUXTBL(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUXTBL(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MUXTBL(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS, uart_mux_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .core_reg[0] = RK3399_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mux_core_alt = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .core_reg[0] = RK3399_CLKSEL_CON(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .mux_core_alt = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mux_core_main = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RK3399_DIV_ACLKM_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RK3399_DIV_ACLKM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define RK3399_DIV_ATCLK_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define RK3399_DIV_ATCLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define RK3399_DIV_PCLK_DBG_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define RK3399_DIV_PCLK_DBG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RK3399_CLKSEL0(_offs, _aclkm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .reg = RK3399_CLKSEL_CON(0 + _offs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RK3399_DIV_ACLKM_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .reg = RK3399_CLKSEL_CON(1 + _offs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RK3399_DIV_ATCLK_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RK3399_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* cluster_l: aclkm in clksel0, rest in clksel1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RK3399_CLKSEL0(0, _aclkm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK3399_CLKSEL1(0, _atclk, _pdbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* cluster_b: aclkm in clksel2, rest in clksel3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .prate = _prate##U, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RK3399_CLKSEL0(2, _aclkm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RK3399_CLKSEL1(2, _atclk, _pdbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * CRU Clock-Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* usbphy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RK3399_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RK3399_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) RK3399_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RK3399_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RK3399_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RK3399_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RK3399_CLKGATE_CON(30), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RK3399_CLKGATE_CON(30), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RK3399_CLKGATE_CON(30), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) RK3399_CLKGATE_CON(30), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RK3399_CLKGATE_CON(30), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RK3399_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RK3399_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RK3399_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RK3399_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RK3399_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) RK3399_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RK3399_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RK3399_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* little core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RK3399_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RK3399_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) RK3399_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RK3399_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RK3399_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) RK3399_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) RK3399_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RK3399_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RK3399_CLKGATE_CON(14), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RK3399_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3399_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RK3399_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RK3399_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* big core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) RK3399_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RK3399_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RK3399_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) RK3399_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK3399_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RK3399_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RK3399_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RK3399_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) RK3399_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) RK3399_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RK3399_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RK3399_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) RK3399_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RK3399_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* gmac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) RK3399_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RK3399_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RK3399_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RK3399_CLKGATE_CON(32), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RK3399_CLKGATE_CON(32), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) RK3399_CLKGATE_CON(32), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) RK3399_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) RK3399_CLKGATE_CON(32), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) RK3399_CLKGATE_CON(32), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) RK3399_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RK3399_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) RK3399_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) RK3399_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) RK3399_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* spdif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) RK3399_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RK3399_CLKSEL_CON(99), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) RK3399_CLKGATE_CON(8), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &rk3399_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) RK3399_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) RK3399_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) RK3399_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) RK3399_CLKSEL_CON(96), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) RK3399_CLKGATE_CON(8), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &rk3399_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RK3399_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK3399_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) RK3399_CLKSEL_CON(97), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) RK3399_CLKGATE_CON(8), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &rk3399_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RK3399_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) RK3399_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RK3399_CLKSEL_CON(98), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) RK3399_CLKGATE_CON(8), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &rk3399_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RK3399_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RK3399_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) RK3399_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RK3399_CLKSEL_CON(100), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) RK3399_CLKGATE_CON(9), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &rk3399_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK3399_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RK3399_CLKSEL_CON(101), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RK3399_CLKGATE_CON(9), 3, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) &rk3399_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RK3399_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RK3399_CLKSEL_CON(102), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RK3399_CLKGATE_CON(9), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) &rk3399_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RK3399_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RK3399_CLKSEL_CON(103), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RK3399_CLKGATE_CON(9), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) &rk3399_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RK3399_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RK3399_CLKGATE_CON(18), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RK3399_CLKGATE_CON(18), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) RK3399_CLKGATE_CON(18), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RK3399_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RK3399_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RK3399_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RK3399_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* cci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RK3399_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RK3399_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(0, "npll_aclk_cci_src", "npll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RK3399_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) RK3399_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RK3399_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) RK3399_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) RK3399_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RK3399_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) RK3399_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) RK3399_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) RK3399_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) RK3399_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) RK3399_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RK3399_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) RK3399_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(0, "cpll_cs", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RK3399_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(0, "gpll_cs", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) RK3399_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(0, "npll_cs", "npll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) RK3399_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) RK3399_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GATE(0, "clk_dbg_noc", "clk_cs", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) RK3399_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* vcodec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RK3399_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RK3399_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) RK3399_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK3399_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RK3399_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) RK3399_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* vdu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) RK3399_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RK3399_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RK3399_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RK3399_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RK3399_CLKGATE_CON(17), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RK3399_CLKGATE_CON(17), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RK3399_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) RK3399_CLKGATE_CON(17), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* iep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) RK3399_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) RK3399_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) RK3399_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) RK3399_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) RK3399_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RK3399_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* rga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) RK3399_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RK3399_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RK3399_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) RK3399_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) RK3399_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RK3399_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) RK3399_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) RK3399_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RK3399_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) RK3399_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* gpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RK3399_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) RK3399_CLKGATE_CON(30), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RK3399_CLKGATE_CON(30), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RK3399_CLKGATE_CON(30), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RK3399_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* perihp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) RK3399_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) RK3399_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) RK3399_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RK3399_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) RK3399_CLKSEL_CON(14), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RK3399_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RK3399_CLKGATE_CON(20), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RK3399_CLKGATE_CON(20), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) RK3399_CLKGATE_CON(20), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RK3399_CLKGATE_CON(20), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) RK3399_CLKGATE_CON(20), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) RK3399_CLKGATE_CON(20), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) RK3399_CLKGATE_CON(20), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK3399_CLKGATE_CON(20), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) RK3399_CLKGATE_CON(20), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) RK3399_CLKGATE_CON(20), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) RK3399_CLKGATE_CON(20), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RK3399_CLKGATE_CON(20), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) RK3399_CLKGATE_CON(20), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RK3399_CLKGATE_CON(31), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* sdio & sdmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) RK3399_CLKGATE_CON(12), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RK3399_CLKGATE_CON(33), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RK3399_CLKGATE_CON(33), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK3399_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RK3399_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* pcie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RK3399_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) RK3399_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RK3399_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* emmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RK3399_CLKGATE_CON(6), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RK3399_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK3399_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) RK3399_CLKGATE_CON(32), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RK3399_CLKGATE_CON(32), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RK3399_CLKGATE_CON(32), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* perilp0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RK3399_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RK3399_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RK3399_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RK3399_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RK3399_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* aclk_perilp0 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* hclk_perilp0 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* pclk_perilp0 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* crypto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) RK3399_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) RK3399_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* cm0s_perilp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) RK3399_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) RK3399_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) RK3399_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* fclk_cm0s gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* perilp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) RK3399_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) RK3399_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) RK3399_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* hclk_perilp1 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(34), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* pclk_perilp1 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* saradc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) RK3399_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* tsadc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) RK3399_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* cif_testout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) RK3399_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) RK3399_CLKGATE_CON(13), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* vio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) RK3399_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) RK3399_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) RK3399_CLKGATE_CON(29), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) RK3399_CLKGATE_CON(29), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RK3399_CLKGATE_CON(29), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) RK3399_CLKGATE_CON(29), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* hdcp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) COMPOSITE_NOGATE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) RK3399_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) RK3399_CLKGATE_CON(11), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) RK3399_CLKGATE_CON(29), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) RK3399_CLKGATE_CON(29), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) RK3399_CLKGATE_CON(29), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) RK3399_CLKGATE_CON(29), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) RK3399_CLKGATE_CON(29), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) RK3399_CLKGATE_CON(29), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) RK3399_CLKGATE_CON(29), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) RK3399_CLKGATE_CON(29), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) RK3399_CLKGATE_CON(29), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* edp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) RK3399_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) RK3399_CLKGATE_CON(11), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RK3399_CLKGATE_CON(32), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) RK3399_CLKGATE_CON(32), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* hdmi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) RK3399_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) RK3399_CLKGATE_CON(11), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* vop0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) RK3399_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) RK3399_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) RK3399_CLKGATE_CON(28), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) RK3399_CLKGATE_CON(28), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) RK3399_CLKGATE_CON(28), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) RK3399_CLKGATE_CON(28), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #ifdef RK3399_TWO_PLL_FOR_VOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) RK3399_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) RK3399_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* The VOP0 is main screen, it is able to re-set parent rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) RK3399_CLKSEL_CON(106), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &rk3399_dclk_vop0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) RK3399_CLKGATE_CON(10), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* vop1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) RK3399_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) RK3399_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) RK3399_CLKGATE_CON(28), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) RK3399_CLKGATE_CON(28), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) RK3399_CLKGATE_CON(28), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) RK3399_CLKGATE_CON(28), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* The VOP1 is sub screen, it is note able to re-set parent rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #ifdef RK3399_TWO_PLL_FOR_VOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) RK3399_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RK3399_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) RK3399_CLKSEL_CON(107), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &rk3399_dclk_vop1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) RK3399_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* isp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) RK3399_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) RK3399_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) RK3399_CLKGATE_CON(27), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) RK3399_CLKGATE_CON(27), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RK3399_CLKGATE_CON(27), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) RK3399_CLKGATE_CON(27), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) RK3399_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) RK3399_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) RK3399_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) RK3399_CLKGATE_CON(27), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "aclk_isp1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) RK3399_CLKGATE_CON(27), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) RK3399_CLKGATE_CON(27), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "hclk_isp1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) RK3399_CLKGATE_CON(27), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) RK3399_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * so we ignore the mux and make clocks nodes as following,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * pclkin_cifinv --|-------\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * pclkin_cif --|-------/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) RK3399_CLKGATE_CON(27), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* cif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) COMPOSITE_NODIV(SCLK_CIF_OUT_SRC, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) RK3399_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* gic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) RK3399_CLKGATE_CON(12), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* alive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 0, RK3399_CLKGATE_CON(21), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* testout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RK3399_CLKSEL_CON(105), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) RK3399_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) DIV(0, "clk_test_24m", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* spi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) RK3399_CLKGATE_CON(9), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) RK3399_CLKGATE_CON(9), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) RK3399_CLKGATE_CON(9), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) RK3399_CLKGATE_CON(9), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) RK3399_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) RK3399_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) RK3399_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) RK3399_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) RK3399_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) RK3399_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) RK3399_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* clk_test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* clk_test_pre is controlled by CRU_MISC_CON[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) RK3399_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* ddrc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * PMU CRU Clock-Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) RK3399_PMU_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) &rk3399_pmuclk_wifi_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) MUX(SCLK_UART4_SRC, "clk_uart4_src", mux_24m_ppll_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) RK3399_PMU_CLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) &rk3399_uart4_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* pmu clock gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IS_CRITICAL, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static void __iomem *rk3399_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static void __iomem *rk3399_pmucru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) void rk3399_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (rk3399_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) 32, 4, rk3399_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) 0x594, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (rk3399_pmucru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) pr_warn("PMU CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) 32, 4, rk3399_pmucru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) 0x134, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) EXPORT_SYMBOL_GPL(rk3399_dump_cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static int rk3399_clk_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) rk3399_dump_cru();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static struct notifier_block rk3399_clk_panic_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .notifier_call = rk3399_clk_panic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static void __init rk3399_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) rk3399_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) rockchip_clk_register_plls(ctx, rk3399_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ARRAY_SIZE(rk3399_pll_clks), -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) rockchip_clk_register_branches(ctx, rk3399_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ARRAY_SIZE(rk3399_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 4, clks[PLL_APLLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ARRAY_SIZE(rk3399_cpuclkl_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) 4, clks[PLL_APLLB], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ARRAY_SIZE(rk3399_cpuclkb_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static void __init rk3399_pmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pr_err("%s: could not map cru pmu region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rk3399_pmucru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) pr_err("%s: rockchip pmu clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ARRAY_SIZE(rk3399_clk_pmu_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) &rk3399_clk_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct clk_rk3399_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .inits = rk3399_pmu_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static const struct clk_rk3399_inits clk_rk3399_cru_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .inits = rk3399_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static const struct of_device_id clk_rk3399_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .compatible = "rockchip,rk3399-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .data = &clk_rk3399_cru_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .compatible = "rockchip,rk3399-pmucru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .data = &clk_rk3399_pmucru_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static int __init clk_rk3399_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) const struct clk_rk3399_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) match = of_match_device(clk_rk3399_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static struct platform_driver clk_rk3399_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .name = "clk-rk3399",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .of_match_table = clk_rk3399_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) MODULE_ALIAS("platform:clk-rk3399");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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