^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/rk3328-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3328_GRF_SOC_CON4 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3328_GRF_SOC_STATUS0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3328_GRF_MAC_CON1 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3328_GRF_MAC_CON2 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum rk3328_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) apll, dpll, cpll, gpll, npll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* vco = 1016064000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* vco = 983040000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* vco = 983040000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* vco = 860156000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* vco = 903168000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* vco = 819200000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RK3328_DIV_ACLKM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RK3328_DIV_ACLKM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK3328_DIV_PCLK_DBG_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RK3328_DIV_PCLK_DBG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .reg = RK3328_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK3328_DIV_ACLKM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3328_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK3328_CPUCLK_RATE(1800000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK3328_CPUCLK_RATE(1704000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3328_CPUCLK_RATE(1608000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK3328_CPUCLK_RATE(1512000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK3328_CPUCLK_RATE(1488000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RK3328_CPUCLK_RATE(1416000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RK3328_CPUCLK_RATE(1392000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RK3328_CPUCLK_RATE(1296000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RK3328_CPUCLK_RATE(1200000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RK3328_CPUCLK_RATE(1104000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RK3328_CPUCLK_RATE(1008000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) RK3328_CPUCLK_RATE(912000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RK3328_CPUCLK_RATE(816000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) RK3328_CPUCLK_RATE(696000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RK3328_CPUCLK_RATE(600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RK3328_CPUCLK_RATE(408000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RK3328_CPUCLK_RATE(312000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RK3328_CPUCLK_RATE(216000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RK3328_CPUCLK_RATE(96000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .core_reg[0] = RK3328_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .mux_core_main = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_pll_p) = { "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_2plls_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "dummy_hdmiphy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_4plls_p) = { "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "dummy_hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "xin24m", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PNAME(mux_armclk_p) = { "apll_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "gpll_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "dpll_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "npll_core"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PNAME(mux_usb480m_p) = { "usb480m_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PNAME(mux_i2s0_p) = { "clk_i2s0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "clk_i2s0_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "xin12m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mux_i2s1_p) = { "clk_i2s1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "clk_i2s1_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "clkin_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mux_i2s2_p) = { "clk_i2s2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "clk_i2s2_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "clkin_i2s2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mux_spdif_p) = { "clk_spdif_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clk_spdif_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "xin12m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PNAME(mux_uart0_p) = { "clk_uart0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "clk_uart0_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PNAME(mux_uart1_p) = { "clk_uart1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "clk_uart1_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PNAME(mux_uart2_p) = { "clk_uart2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "clk_uart2_frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PNAME(mux_sclk_cif_p) = { "clk_cif_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PNAME(mux_dclk_lcdc_p) = { "hdmiphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "dclk_lcdc_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "gpll_peri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "hdmiphy_peri" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "clk_usb3otg_ref" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mux_xin24m_32k_p) = { "xin24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "clk_rtc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "gmac_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "phy_50m_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "gmac_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0, RK3328_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0, RK3328_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK3328_MODE_CON, 4, 3, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0, RK3328_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0, RK3328_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0, RK3328_PLL_CON(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RK3328_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* PD_MISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RK3328_MISC_CON, 13, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RK3328_MISC_CON, 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RK3328_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) RK3328_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RK3328_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RK3328_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) RK3328_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RK3328_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GATE(0, "aclk_core_niu", "aclk_core", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RK3328_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GATE(0, "aclk_gic400", "aclk_core", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RK3328_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) GATE(0, "clk_jtag", "jtag_clkin", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) RK3328_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* PD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK3328_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) RK3328_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK3328_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RK3328_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RK3328_CLKGATE_CON(18), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RK3328_CLKGATE_CON(18), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK3328_CLKGATE_CON(18), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RK3328_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK3328_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) RK3328_CLKGATE_CON(18), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) RK3328_CLKGATE_CON(18), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RK3328_CLKGATE_CON(18), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RK3328_CLKGATE_CON(18), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RK3328_CLKGATE_CON(18), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK3328_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RK3328_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RK3328_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GATE(0, "pclk_bus", "pclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RK3328_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK3328_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK3328_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RK3328_CLKGATE_CON(17), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* PD_I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RK3328_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RK3328_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) RK3328_CLKGATE_CON(1), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &rk3328_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RK3328_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RK3328_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RK3328_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RK3328_CLKGATE_CON(1), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &rk3328_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RK3328_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RK3328_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RK3328_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RK3328_CLKSEL_CON(11), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RK3328_CLKGATE_CON(1), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &rk3328_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RK3328_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RK3328_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RK3328_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RK3328_CLKSEL_CON(13), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RK3328_CLKGATE_CON(1), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &rk3328_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* PD_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RK3328_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RK3328_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RK3328_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RK3328_CLKSEL_CON(15), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) RK3328_CLKGATE_CON(1), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &rk3328_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) RK3328_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RK3328_CLKGATE_CON(2), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &rk3328_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RK3328_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RK3328_CLKGATE_CON(2), 3, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &rk3328_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RK3328_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RK3328_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RK3328_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) RK3328_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RK3328_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RK3328_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RK3328_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) RK3328_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RK3328_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RK3328_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RK3328_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RK3328_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RK3328_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) RK3328_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RK3328_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RK3328_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RK3328_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RK3328_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RK3328_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* PD_VIDEO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RK3328_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RK3328_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) RK3328_CLKGATE_CON(24), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RK3328_CLKGATE_CON(24), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RK3328_CLKGATE_CON(24), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RK3328_CLKGATE_CON(24), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) RK3328_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RK3328_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RK3328_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RK3328_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RK3328_CLKGATE_CON(23), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) RK3328_CLKGATE_CON(23), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RK3328_CLKGATE_CON(23), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RK3328_CLKGATE_CON(23), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) RK3328_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RK3328_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) FACTOR_GATE(0, "hclk_venc", "sclk_venc_core", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RK3328_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(0, "aclk_rkvenc_niu", "sclk_venc_core", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RK3328_CLKGATE_CON(25), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(0, "hclk_rkvenc_niu", "hclk_venc", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) RK3328_CLKGATE_CON(25), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GATE(ACLK_H265, "aclk_h265", "sclk_venc_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RK3328_CLKGATE_CON(25), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(PCLK_H265, "pclk_h265", "hclk_venc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) RK3328_CLKGATE_CON(25), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GATE(ACLK_H264, "aclk_h264", "sclk_venc_core", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) RK3328_CLKGATE_CON(25), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(HCLK_H264, "hclk_h264", "hclk_venc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) RK3328_CLKGATE_CON(25), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(ACLK_AXISRAM, "aclk_axisram", "sclk_venc_core", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) RK3328_CLKGATE_CON(25), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) RK3328_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* PD_VIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RK3328_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RK3328_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RK3328_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RK3328_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RK3328_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) RK3328_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) RK3328_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Clock-Architecture Diagram 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(0, "gpll_peri", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RK3328_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(0, "cpll_peri", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RK3328_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) RK3328_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) RK3328_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) RK3328_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) RK3328_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RK3328_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RK3328_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RK3328_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) RK3328_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) RK3328_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RK3328_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RK3328_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Clock-Architecture Diagram 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RK3328_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) RK3328_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) RK3328_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) RK3328_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RK3328_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) RK3328_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RK3328_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) RK3328_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK3328_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) RK3328_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RK3328_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RK3328_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* PD_VOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) GATE(0, "aclk_rga_niu", "aclk_rga_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GATE(0, "aclk_vop_niu", "aclk_vop_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GATE(0, "aclk_vio_niu", "aclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) GATE(0, "hclk_vop_niu", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) GATE(0, "hclk_vio_niu", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(0, "pclk_peri_niu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GATE(0, "aclk_gmac_niu", "aclk_gmac", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(26), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(0, "pclk_gmac_niu", "pclk_gmac", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(26), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(0, "pclk_cru", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GATE(0, "pclk_sgrf", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(0, "pclk_pmu", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(28), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Watchdog pclk is controlled from the secure GRF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* PD_MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) RK3328_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RK3328_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RK3328_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) RK3328_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) RK3328_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RK3328_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK3328_SDMMC_EXT_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RK3328_SDMMC_EXT_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static void __init rk3328_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rockchip_clk_register_plls(ctx, rk3328_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ARRAY_SIZE(rk3328_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RK3328_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) rockchip_clk_register_branches(ctx, rk3328_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ARRAY_SIZE(rk3328_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 4, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &rk3328_cpuclk_data, rk3328_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ARRAY_SIZE(rk3328_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int __init clk_rk3328_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rk3328_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct of_device_id clk_rk3328_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .compatible = "rockchip,rk3328-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MODULE_DEVICE_TABLE(of, clk_rk3328_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static struct platform_driver clk_rk3328_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .name = "clk-rk3328",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .of_match_table = clk_rk3328_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) builtin_platform_driver_probe(clk_rk3328_driver, clk_rk3328_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MODULE_DESCRIPTION("Rockchip RK3328 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags