^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/rk3288-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/psci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3288_GRF_SOC_STATUS1 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum rk3288_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RK3288_CRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RK3288W_CRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum rk3288_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) apll, dpll, cpll, gpll, npll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3066_PLL_RATE(2208000000, 1, 92, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3066_PLL_RATE(2184000000, 1, 91, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3066_PLL_RATE(2160000000, 1, 90, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3066_PLL_RATE(2136000000, 1, 89, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3066_PLL_RATE(2112000000, 1, 88, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3066_PLL_RATE(2088000000, 1, 87, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3066_PLL_RATE(2064000000, 1, 86, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3066_PLL_RATE(2040000000, 1, 85, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3066_PLL_RATE(2016000000, 1, 84, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3066_PLL_RATE(1992000000, 1, 83, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3066_PLL_RATE(1968000000, 1, 82, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3066_PLL_RATE(1944000000, 1, 81, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3066_PLL_RATE(1920000000, 1, 80, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3066_PLL_RATE(1896000000, 1, 79, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3066_PLL_RATE(1872000000, 1, 78, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3066_PLL_RATE(1848000000, 1, 77, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3066_PLL_RATE(1824000000, 1, 76, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3066_PLL_RATE(1800000000, 1, 75, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3066_PLL_RATE(1776000000, 1, 74, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3066_PLL_RATE(1752000000, 1, 73, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3066_PLL_RATE(1728000000, 1, 72, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3066_PLL_RATE(1704000000, 1, 71, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3066_PLL_RATE(1680000000, 1, 70, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3066_PLL_RATE(1656000000, 1, 69, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3066_PLL_RATE(1632000000, 1, 68, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3066_PLL_RATE(1608000000, 1, 67, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3066_PLL_RATE(1560000000, 1, 65, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3066_PLL_RATE(1512000000, 1, 63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3066_PLL_RATE(1488000000, 1, 62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3066_PLL_RATE(1464000000, 1, 61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3066_PLL_RATE(1440000000, 1, 60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3066_PLL_RATE(1416000000, 1, 59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3066_PLL_RATE(1392000000, 1, 58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3066_PLL_RATE(1368000000, 1, 57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3066_PLL_RATE(1344000000, 1, 56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3066_PLL_RATE(1320000000, 1, 55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3066_PLL_RATE(1296000000, 1, 54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3066_PLL_RATE(1272000000, 1, 53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3066_PLL_RATE(1248000000, 1, 52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3066_PLL_RATE(1224000000, 1, 51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3066_PLL_RATE(1200000000, 1, 50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3066_PLL_RATE(1188000000, 1, 99, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3066_PLL_RATE(1176000000, 1, 49, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3066_PLL_RATE(1128000000, 1, 47, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3066_PLL_RATE(1104000000, 1, 46, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3066_PLL_RATE(1008000000, 1, 84, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3066_PLL_RATE( 912000000, 1, 76, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3066_PLL_RATE( 891000000, 2, 297, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3066_PLL_RATE( 888000000, 1, 74, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3066_PLL_RATE( 816000000, 1, 68, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3066_PLL_RATE( 798000000, 1, 133, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3066_PLL_RATE( 792000000, 1, 66, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3066_PLL_RATE( 768000000, 1, 64, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3066_PLL_RATE( 742500000, 4, 495, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3066_PLL_RATE( 696000000, 1, 58, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3066_PLL_RATE( 600000000, 1, 50, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3066_PLL_RATE( 552000000, 1, 46, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK3066_PLL_RATE( 504000000, 1, 84, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK3066_PLL_RATE( 500000000, 1, 125, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RK3066_PLL_RATE( 456000000, 1, 76, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RK3066_PLL_RATE( 428000000, 1, 107, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK3066_PLL_RATE( 408000000, 1, 68, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK3066_PLL_RATE( 400000000, 1, 100, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) RK3066_PLL_RATE( 384000000, 1, 64, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RK3066_PLL_RATE( 360000000, 1, 60, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3066_PLL_RATE( 312000000, 1, 52, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK3066_PLL_RATE( 300000000, 1, 75, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK3066_PLL_RATE( 297000000, 1, 99, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RK3066_PLL_RATE( 273600000, 1, 114, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK3066_PLL_RATE( 252000000, 1, 84, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK3066_PLL_RATE( 238000000, 1, 119, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RK3066_PLL_RATE( 195428571, 1, 114, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RK3066_PLL_RATE( 160000000, 1, 80, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RK3066_PLL_RATE( 157500000, 1, 105, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) RK3066_PLL_RATE( 148500000, 1, 99, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RK3066_PLL_RATE( 126000000, 1, 84, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RK3288_DIV_ACLK_CORE_MP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RK3288_DIV_L2RAM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RK3288_DIV_L2RAM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RK3288_DIV_ATCLK_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RK3288_DIV_ATCLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RK3288_DIV_PCLK_DBGPRE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RK3288_CLKSEL0(_core_m0, _core_mp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .reg = RK3288_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RK3288_DIV_ACLK_CORE_MP_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .reg = RK3288_CLKSEL_CON(37), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) RK3288_DIV_L2RAM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RK3288_DIV_ATCLK_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) HIWORD_UPDATE(_pclk_dbg_pre, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RK3288_DIV_PCLK_DBGPRE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) RK3288_DIV_PCLK_DBGPRE_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RK3288_CLKSEL0(_core_m0, _core_mp), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .core_reg[0] = RK3288_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .div_core_shift[0] = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .mux_core_shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PNAME(mux_pll_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "sclk_otgphy0_480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RK3288_MODE_CON, 4, 5, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct clk_div_table div_hclk_cpu_t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { /* sentinel */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) RK3288_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) RK3288_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) RK3288_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RK3288_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) RK3288_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) RK3288_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) RK3288_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK3288_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RK3288_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RK3288_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RK3288_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RK3288_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RK3288_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK3288_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RK3288_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) GATE(0, "gpll_ddr", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) RK3288_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GATE(0, "gpll_aclk_cpu", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RK3288_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GATE(0, "cpll_aclk_cpu", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RK3288_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) RK3288_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RK3288_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK3288_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) GATE(0, "c2c_host", "aclk_cpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK3288_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RK3288_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RK3288_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RK3288_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) RK3288_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RK3288_CLKGATE_CON(4), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &rk3288_i2s_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RK3288_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RK3288_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) RK3288_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RK3288_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RK3288_CLKGATE_CON(4), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) &rk3288_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) RK3288_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RK3288_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) RK3288_CLKSEL_CON(41), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RK3288_CLKGATE_CON(4), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) &rk3288_spdif_8ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RK3288_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GATE(0, "sclk_acc_efuse", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) RK3288_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) RK3288_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RK3288_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RK3288_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RK3288_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RK3288_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RK3288_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RK3288_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK3288_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RK3288_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RK3288_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RK3288_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RK3288_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RK3288_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) RK3288_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RK3288_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RK3288_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) RK3288_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RK3288_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RK3288_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RK3288_CLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RK3288_CLKGATE_CON(3), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RK3288_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RK3288_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RK3288_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) RK3288_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RK3288_CLKGATE_CON(13), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) RK3288_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) COMPOSITE_NOMUX(PCLK_PD_PMU, "pclk_pd_pmu", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RK3288_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RK3288_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) RK3288_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RK3288_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RK3288_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RK3288_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RK3288_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RK3288_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) RK3288_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) RK3288_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) RK3288_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) RK3288_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) RK3288_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) RK3288_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RK3288_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) RK3288_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) RK3288_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RK3288_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RK3288_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) RK3288_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) RK3288_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) RK3288_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) RK3288_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RK3288_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RK3288_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RK3288_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK3288_CLKGATE_CON(1), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &rk3288_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RK3288_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) RK3288_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RK3288_CLKGATE_CON(1), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &rk3288_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RK3288_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) RK3288_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RK3288_CLKGATE_CON(1), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &rk3288_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) RK3288_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) RK3288_CLKSEL_CON(20), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RK3288_CLKGATE_CON(1), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &rk3288_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RK3288_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RK3288_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) RK3288_CLKGATE_CON(2), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &rk3288_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RK3288_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RK3288_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RK3288_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) RK3288_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) RK3288_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) RK3288_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RK3288_CLKSEL_CON(22), 7, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GATE(0, "jtag", "ext_jtag", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RK3288_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RK3288_CLKGATE_CON(5), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) RK3288_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) RK3288_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* aclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* hclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* pclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(11), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* ddrctrl [DDR Controller PHY clock] gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* ddrphy gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* aclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* hclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GATE(0, "pmu_hclk_otg0", "hclk_peri", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* pclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* sclk_gpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* pclk_pd_alive gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* pclk_pd_pmu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* hclk_vio gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* aclk_vio0 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* aclk_vio1 gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* aclk_rga_pre gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(15), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * Other ungrouped clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) DIV(0, "hclk_vio", "aclk_vio1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) DIV(0, "hclk_vio", "aclk_vio0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void __iomem *rk3288_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * Some CRU registers will be reset in maskrom when the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * wakes up from fastboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * So save them before suspend, restore them after resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const int rk3288_saved_cru_reg_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RK3288_MODE_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RK3288_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RK3288_CLKSEL_CON(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RK3288_CLKSEL_CON(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RK3288_CLKSEL_CON(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) RK3288_CLKSEL_CON(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* We turn aclk_dmac1 on for suspend; this will restore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) RK3288_CLKGATE_CON(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int rk3288_clk_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int i, reg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) reg_id = rk3288_saved_cru_reg_ids[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rk3288_saved_cru_regs[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) readl_relaxed(rk3288_cru_base + reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Going into deep sleep (specifically setting PMU_CLR_DMA in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * RK3288_PMU_PWRMODE_CON1) appears to fail unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * "aclk_dmac1" is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writel_relaxed(1 << (12 + 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) rk3288_cru_base + RK3288_CLKGATE_CON(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Switch PLLs other than DPLL (for SDRAM) to slow mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * avoid crashes on resume. The Mask ROM on the system will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * put APLL, CPLL, and GPLL into slow mode at resume time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * anyway (which is why we restore them), but we might not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * even make it to the Mask ROM if this isn't done at suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * NOTE: only APLL truly matters here, but we'll do them all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static void rk3288_clk_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int i, reg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) reg_id = rk3288_saved_cru_reg_ids[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) rk3288_cru_base + reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void rk3288_clk_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct syscore_ops rk3288_clk_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .suspend = rk3288_clk_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .resume = rk3288_clk_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static void rk3288_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (rk3288_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) 32, 4, rk3288_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) 0x21c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static void __init rk3288_common_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) enum rk3288_variant soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rk3288_cru_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (!rk3288_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) iounmap(rk3288_cru_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) rockchip_clk_register_plls(ctx, rk3288_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ARRAY_SIZE(rk3288_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK3288_GRF_SOC_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) rockchip_clk_register_branches(ctx, rk3288_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ARRAY_SIZE(rk3288_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (soc == RK3288W_CRU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ARRAY_SIZE(rk3288w_hclkvio_branch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ARRAY_SIZE(rk3288_hclkvio_branch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) 2, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &rk3288_cpuclk_data, rk3288_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ARRAY_SIZE(rk3288_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) rockchip_register_softrst(np, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rk3288_cru_base + RK3288_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) rk3288_clk_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!psci_smp_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) register_syscore_ops(&rk3288_clk_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!rk_dump_cru)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) rk_dump_cru = rk3288_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void __init rk3288_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) rk3288_common_init(np, RK3288_CRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void __init rk3288w_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) rk3288_common_init(np, RK3288W_CRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct clk_rk3288_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const struct clk_rk3288_inits clk_rk3288_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .inits = rk3288_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const struct clk_rk3288_inits clk_rk3288w_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .inits = rk3288w_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const struct of_device_id clk_rk3288_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .compatible = "rockchip,rk3288-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .data = &clk_rk3288_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .compatible = "rockchip,rk3288w-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .data = &clk_rk3288w_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) MODULE_DEVICE_TABLE(of, clk_rk3288_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int __init clk_rk3288_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) const struct clk_rk3288_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) match = of_match_device(clk_rk3288_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static struct platform_driver clk_rk3288_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .name = "clk-rk3288",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .of_match_table = clk_rk3288_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) builtin_platform_driver_probe(clk_rk3288_driver, clk_rk3288_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) MODULE_DESCRIPTION("Rockchip RK3288 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags