^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jeffy Chen <jeffy.chen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/rk3228-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3228_GRF_SOC_STATUS0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum rk3228_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) apll, dpll, cpll, gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RK3228_DIV_CPU_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RK3228_DIV_CPU_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RK3228_DIV_PERI_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RK3228_DIV_PERI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK3228_DIV_ACLK_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK3228_DIV_ACLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK3228_DIV_HCLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK3228_DIV_HCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK3228_DIV_PCLK_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK3228_DIV_PCLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg = RK2928_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3228_DIV_PERI_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3228_DIV_ACLK_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3228_CPUCLK_RATE(1800000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK3228_CPUCLK_RATE(1704000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK3228_CPUCLK_RATE(1608000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK3228_CPUCLK_RATE(1512000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK3228_CPUCLK_RATE(1488000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK3228_CPUCLK_RATE(1464000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RK3228_CPUCLK_RATE(1416000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK3228_CPUCLK_RATE(1392000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RK3228_CPUCLK_RATE(1296000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK3228_CPUCLK_RATE(1200000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK3228_CPUCLK_RATE(1104000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RK3228_CPUCLK_RATE(1008000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK3228_CPUCLK_RATE(912000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK3228_CPUCLK_RATE(816000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3228_CPUCLK_RATE(696000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK3228_CPUCLK_RATE(600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK3228_CPUCLK_RATE(408000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RK3228_CPUCLK_RATE(312000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RK3228_CPUCLK_RATE(216000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) RK3228_CPUCLK_RATE(96000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .core_reg[0] = RK2928_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RK2928_MODE_CON, 4, 6, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RK2928_MODE_CON, 8, 8, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK2928_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RK2928_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RK2928_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RK2928_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK2928_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RK2928_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RK2928_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RK2928_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) RK2928_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RK2928_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) RK2928_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* PD_MISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) RK2928_MISC_CON, 13, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) RK2928_MISC_CON, 14, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RK2928_MISC_CON, 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RK2928_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GATE(0, "gpll_aclk_cpu", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RK2928_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GATE(0, "cpll_aclk_cpu", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) RK2928_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) RK2928_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RK2928_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RK2928_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RK2928_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GATE(0, "pclk_phy_pre", "pclk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) RK2928_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GATE(0, "pclk_ddr_pre", "pclk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RK2928_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* PD_VIDEO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) RK2928_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) RK2928_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) RK2928_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) RK2928_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) RK2928_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RK2928_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* PD_VIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) RK2928_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RK2928_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK2928_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RK2928_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RK2928_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK2928_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RK2928_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RK2928_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GATE(0, "cpll_peri", "cpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GATE(0, "gpll_peri", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) RK2928_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RK2928_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK2928_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RK2928_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RK2928_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RK2928_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RK2928_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RK2928_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RK2928_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) RK2928_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RK2928_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) RK2928_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) RK2928_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) RK2928_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) RK2928_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RK2928_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GATE(0, "gpll_vop", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RK2928_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) GATE(0, "cpll_vop", "cpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RK2928_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RK2928_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RK2928_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK2928_CLKGATE_CON(0), 4, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &rk3228_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) RK2928_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RK2928_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RK2928_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RK2928_CLKGATE_CON(0), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &rk3228_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RK2928_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RK2928_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RK2928_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) RK2928_CLKSEL_CON(30), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RK2928_CLKGATE_CON(0), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &rk3228_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RK2928_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RK2928_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RK2928_CLKSEL_CON(20), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RK2928_CLKGATE_CON(2), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &rk3228_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RK2928_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RK2928_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RK2928_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RK2928_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RK2928_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RK2928_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* PD_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RK2928_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RK2928_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0, RK2928_CLKSEL_CON(15), 12, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) RK2928_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RK2928_CLKGATE_CON(1), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &rk3228_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RK2928_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RK2928_CLKGATE_CON(1), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &rk3228_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RK2928_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) RK2928_CLKGATE_CON(1), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &rk3228_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RK2928_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) RK2928_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) RK2928_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RK2928_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) RK2928_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RK2928_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RK2928_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RK2928_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* PD_VOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* PD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(7), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GATE(0, "aclk_initmem", "aclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GATE(0, "hclk_rom", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GATE(0, "pclk_stimer", "pclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GATE(0, "pclk_sim", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* PD_MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void __iomem *rk3228_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void rk3228_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (rk3228_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 32, 4, rk3228_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x1f8, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void __init rk3228_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rockchip_clk_register_plls(ctx, rk3228_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ARRAY_SIZE(rk3228_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RK3228_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) rockchip_clk_register_branches(ctx, rk3228_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ARRAY_SIZE(rk3228_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 3, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &rk3228_cpuclk_data, rk3228_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ARRAY_SIZE(rk3228_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!rk_dump_cru) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) rk3228_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rk_dump_cru = rk3228_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int __init clk_rk3228_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) rk3228_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const struct of_device_id clk_rk3228_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .compatible = "rockchip,rk3228-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) MODULE_DEVICE_TABLE(of, clk_rk3228_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static struct platform_driver clk_rk3228_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .name = "clk-rk3228",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .of_match_table = clk_rk3228_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) builtin_platform_driver_probe(clk_rk3228_driver, clk_rk3228_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MODULE_DESCRIPTION("Rockchip RK3228 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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