^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/rk3188-cru-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3066_GRF_SOC_STATUS 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3188_GRF_SOC_STATUS 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum rk3188_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) apll, cpll, dpll, gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RK3066_PLL_RATE(2208000000, 1, 92, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RK3066_PLL_RATE(2184000000, 1, 91, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RK3066_PLL_RATE(2160000000, 1, 90, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3066_PLL_RATE(2136000000, 1, 89, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3066_PLL_RATE(2112000000, 1, 88, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3066_PLL_RATE(2088000000, 1, 87, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3066_PLL_RATE(2064000000, 1, 86, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3066_PLL_RATE(2040000000, 1, 85, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3066_PLL_RATE(2016000000, 1, 84, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3066_PLL_RATE(1992000000, 1, 83, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3066_PLL_RATE(1968000000, 1, 82, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3066_PLL_RATE(1944000000, 1, 81, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3066_PLL_RATE(1920000000, 1, 80, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3066_PLL_RATE(1896000000, 1, 79, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3066_PLL_RATE(1872000000, 1, 78, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3066_PLL_RATE(1848000000, 1, 77, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3066_PLL_RATE(1824000000, 1, 76, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3066_PLL_RATE(1800000000, 1, 75, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3066_PLL_RATE(1776000000, 1, 74, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3066_PLL_RATE(1752000000, 1, 73, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3066_PLL_RATE(1728000000, 1, 72, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3066_PLL_RATE(1704000000, 1, 71, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3066_PLL_RATE(1680000000, 1, 70, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3066_PLL_RATE(1656000000, 1, 69, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3066_PLL_RATE(1632000000, 1, 68, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3066_PLL_RATE(1608000000, 1, 67, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3066_PLL_RATE(1560000000, 1, 65, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3066_PLL_RATE(1512000000, 1, 63, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3066_PLL_RATE(1488000000, 1, 62, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3066_PLL_RATE(1464000000, 1, 61, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3066_PLL_RATE(1440000000, 1, 60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3066_PLL_RATE(1416000000, 1, 59, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3066_PLL_RATE(1392000000, 1, 58, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3066_PLL_RATE(1368000000, 1, 57, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3066_PLL_RATE(1344000000, 1, 56, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3066_PLL_RATE(1320000000, 1, 55, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3066_PLL_RATE(1296000000, 1, 54, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3066_PLL_RATE(1272000000, 1, 53, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3066_PLL_RATE(1248000000, 1, 52, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3066_PLL_RATE(1224000000, 1, 51, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3066_PLL_RATE(1200000000, 1, 50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3066_PLL_RATE(1188000000, 2, 99, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3066_PLL_RATE(1176000000, 1, 49, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3066_PLL_RATE(1128000000, 1, 47, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3066_PLL_RATE(1104000000, 1, 46, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3066_PLL_RATE(1008000000, 1, 84, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3066_PLL_RATE( 912000000, 1, 76, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3066_PLL_RATE( 891000000, 8, 594, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3066_PLL_RATE( 888000000, 1, 74, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3066_PLL_RATE( 816000000, 1, 68, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RK3066_PLL_RATE( 798000000, 2, 133, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RK3066_PLL_RATE( 792000000, 1, 66, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RK3066_PLL_RATE( 768000000, 1, 64, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) RK3066_PLL_RATE( 742500000, 8, 495, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RK3066_PLL_RATE( 696000000, 1, 58, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RK3066_PLL_RATE( 600000000, 1, 50, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) RK3066_PLL_RATE( 594000000, 2, 198, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RK3066_PLL_RATE( 552000000, 1, 46, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) RK3066_PLL_RATE( 504000000, 1, 84, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) RK3066_PLL_RATE( 456000000, 1, 76, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RK3066_PLL_RATE( 408000000, 1, 68, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RK3066_PLL_RATE( 400000000, 3, 100, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK3066_PLL_RATE( 384000000, 2, 128, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RK3066_PLL_RATE( 360000000, 1, 60, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3066_PLL_RATE( 312000000, 1, 52, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RK3066_PLL_RATE( 300000000, 1, 50, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RK3066_PLL_RATE( 297000000, 2, 198, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RK3066_PLL_RATE( 252000000, 1, 84, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RK3066_PLL_RATE( 216000000, 1, 72, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RK3066_PLL_RATE( 148500000, 2, 99, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RK3066_PLL_RATE( 126000000, 1, 84, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3066_PLL_RATE( 48000000, 1, 64, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RK3066_DIV_CORE_PERIPH_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RK3066_DIV_CORE_PERIPH_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RK3066_DIV_ACLK_CORE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RK3066_DIV_ACLK_CORE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RK3066_DIV_ACLK_HCLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RK3066_DIV_ACLK_HCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RK3066_DIV_ACLK_PCLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RK3066_DIV_ACLK_PCLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RK3066_DIV_AHB2APB_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RK3066_DIV_AHB2APB_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RK3066_CLKSEL0(_core_peri) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .reg = RK2928_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK3066_DIV_CORE_PERIPH_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .reg = RK2928_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RK3066_DIV_ACLK_CORE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RK3066_DIV_ACLK_HCLK_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RK3066_DIV_ACLK_PCLK_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RK3066_DIV_AHB2APB_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RK3066_CLKSEL0(_core_peri), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .core_reg[0] = RK2928_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mux_core_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RK3188_DIV_ACLK_CORE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RK3188_DIV_ACLK_CORE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RK3188_CLKSEL1(_aclk_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .reg = RK2928_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RK3188_DIV_ACLK_CORE_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RK3066_CLKSEL0(_core_peri), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RK3188_CLKSEL1(_aclk_core), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RK3188_CPUCLK_RATE(1608000000, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RK3188_CPUCLK_RATE(1416000000, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RK3188_CPUCLK_RATE(1200000000, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RK3188_CPUCLK_RATE(1008000000, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RK3188_CPUCLK_RATE( 816000000, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) RK3188_CPUCLK_RATE( 600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RK3188_CPUCLK_RATE( 504000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) RK3188_CPUCLK_RATE( 312000000, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .core_reg[0] = RK2928_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .div_core_shift[0] = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mux_core_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PNAME(mux_pll_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PNAME(mux_mac_p) = { "gpll", "dpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) RK2928_MODE_CON, 4, 4, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK2928_MODE_CON, 4, 5, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 2 ^ (val + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct clk_div_table div_core_peri_t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { .val = 1, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .val = 2, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { .val = 3, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct rockchip_clk_branch common_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct rockchip_clk_branch common_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct rockchip_clk_branch common_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct rockchip_clk_branch common_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct rockchip_clk_branch common_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct rockchip_clk_branch common_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* these two are set by the cpuclk and should not be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) RK2928_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) RK2928_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RK2928_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RK2928_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RK2928_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RK2928_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) RK2928_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RK2928_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RK2928_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK2928_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK2928_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RK2928_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RK2928_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RK2928_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RK2928_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RK2928_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) GATE(0, "pclkin_cif0", "ext_cif0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RK2928_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) INVERTER(0, "pclk_cif0", "pclkin_cif0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RK2928_CLKSEL_CON(30), 8, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * the 480m are generated inside the usb block from these clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * but they are also a source for the hsicphy clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) RK2928_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK2928_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) COMPOSITE(0, "mac_src", mux_mac_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RK2928_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GATE(0, "sclk_mac_lbtest", "sclk_macref", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RK2928_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RK2928_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK2928_CLKSEL_CON(23), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) RK2928_CLKGATE_CON(2), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) &common_hsadc_out_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RK2928_CLKSEL_CON(22), 7, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) RK2928_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) RK2928_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) RK2928_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) RK2928_CLKGATE_CON(0), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) &common_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RK2928_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RK2928_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) RK2928_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) RK2928_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RK2928_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RK2928_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RK2928_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RK2928_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RK2928_CLKGATE_CON(1), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &common_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RK2928_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) RK2928_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK2928_CLKGATE_CON(1), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &common_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RK2928_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) RK2928_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RK2928_CLKGATE_CON(1), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &common_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RK2928_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RK2928_CLKSEL_CON(20), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RK2928_CLKGATE_CON(1), 15, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &common_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* clk_core_pre gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* aclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* hclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) GATE(0, "hclk_cpubus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* hclk_ahb2apb is part of a clk branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GATE(0, "hclk_vio_bus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* hclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* aclk_lcdc0_pre gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* aclk_lcdc1_pre gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* atclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* pclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* aclk_peri */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* pclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct clk_div_table div_aclk_cpu_t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { .val = 4, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) | CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) | CLK_DIVIDER_READ_ONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) RK2928_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RK2928_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RK2928_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RK2928_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK2928_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GATE(0, "pclkin_cif1", "ext_cif1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RK2928_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) INVERTER(0, "pclk_cif1", "pclkin_cif1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) RK2928_CLKSEL_CON(30), 12, IFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) RK2928_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RK2928_CLKGATE_CON(5), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) RK2928_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) RK2928_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RK2928_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) RK2928_CLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RK2928_CLKGATE_CON(0), 8, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &rk3066a_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RK2928_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RK2928_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RK2928_CLKGATE_CON(0), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &rk3066a_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) RK2928_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RK2928_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) RK2928_CLKGATE_CON(0), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &rk3066a_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) RK2928_CLKGATE_CON(5), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct clk_div_table div_rk3188_aclk_core_t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .val = 4, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* do not source aclk_cpu_pre from the apll, to keep complexity down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) COMPOSITE_NOGATE(ACLK_CPU_PRE, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) RK2928_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RK2928_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) RK2928_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) RK2928_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RK2928_CLKGATE_CON(3), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) RK2928_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RK2928_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK2928_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RK2928_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RK2928_CLKGATE_CON(0), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) &rk3188_i2s0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RK2928_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rockchip_clk_register_branches(ctx, common_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ARRAY_SIZE(common_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static void __init rk3066a_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ctx = rk3188_common_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (IS_ERR(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rockchip_clk_register_plls(ctx, rk3066_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ARRAY_SIZE(rk3066_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RK3066_GRF_SOC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ARRAY_SIZE(rk3066a_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 2, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) &rk3066_cpuclk_data, rk3066_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ARRAY_SIZE(rk3066_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void __init rk3188a_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ctx = rk3188_common_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (IS_ERR(ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) rockchip_clk_register_plls(ctx, rk3188_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ARRAY_SIZE(rk3188_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RK3188_GRF_SOC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) rockchip_clk_register_branches(ctx, rk3188_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ARRAY_SIZE(rk3188_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 2, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &rk3188_cpuclk_data, rk3188_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ARRAY_SIZE(rk3188_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* reparent aclk_cpu_pre from apll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) rate = clk_get_rate(clks[ACLK_CPU_PRE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk_set_rate(clks[ACLK_CPU_PRE], rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void __init rk3188_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct rockchip_pll_rate_table *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!pll->rate_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rate = pll->rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) while (rate->rate > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) rate->nb = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) rate++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) rk3188a_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct clk_rk3188_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct clk_rk3188_inits clk_rk3066a_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .inits = rk3066a_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const struct clk_rk3188_inits clk_rk3188a_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .inits = rk3188a_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct clk_rk3188_inits clk_rk3188_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .inits = rk3188_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const struct of_device_id clk_rk3188_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .compatible = "rockchip,rk3066a-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .data = &clk_rk3066a_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .compatible = "rockchip,rk3188a-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .data = &clk_rk3188a_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .compatible = "rockchip,rk3188-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .data = &rk3188_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_DEVICE_TABLE(of, clk_rk3188_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int __init clk_rk3188_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) const struct clk_rk3188_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) match = of_match_device(clk_rk3188_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static struct platform_driver clk_rk3188_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .name = "clk-rk3188",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .of_match_table = clk_rk3188_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) builtin_platform_driver_probe(clk_rk3188_driver, clk_rk3188_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MODULE_DESCRIPTION("Rockchip RK3188 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags