^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xing Zheng <zhengxing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/rk3036-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3036_GRF_SOC_STATUS0 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum rk3036_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) apll, dpll, gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RK3036_DIV_CPU_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RK3036_DIV_CPU_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RK3036_DIV_PERI_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RK3036_DIV_PERI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK3036_DIV_ACLK_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK3036_DIV_ACLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK3036_DIV_HCLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK3036_DIV_HCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RK3036_DIV_PCLK_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK3036_DIV_PCLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RK3036_CLKSEL1(_core_periph_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg = RK2928_CLKSEL_CON(1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK3036_DIV_PERI_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK3036_CLKSEL1(_core_periph_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK3036_CPUCLK_RATE(1200000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK3036_CPUCLK_RATE(1008000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK3036_CPUCLK_RATE(816000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK3036_CPUCLK_RATE(600000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK3036_CPUCLK_RATE(408000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK3036_CPUCLK_RATE(312000000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .core_reg[0] = RK2928_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .div_core_mask[0] = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .mux_core_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PNAME(mux_pll_p) = { "xin24m", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RK2928_MODE_CON, 4, 4, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MUX(SCLK_I2S_PRE, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RK2928_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) RK2928_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RK2928_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RK2928_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) RK2928_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) GATE(0, "dpll_cpu", "dpll", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GATE(0, "gpll_cpu", "gpll", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) RK2928_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RK2928_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) RK2928_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) RK2928_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) RK2928_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) RK2928_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RK2928_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) RK2928_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RK2928_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) RK2928_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) RK2928_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) RK2928_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) RK2928_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) RK2928_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RK2928_CLKSEL_CON(17), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) RK2928_CLKGATE_CON(1), 9, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) &rk3036_uart0_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RK2928_CLKSEL_CON(18), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) RK2928_CLKGATE_CON(1), 11, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &rk3036_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) RK2928_CLKSEL_CON(19), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) RK2928_CLKGATE_CON(1), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) &rk3036_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RK2928_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) RK2928_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RK2928_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) RK2928_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) RK2928_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RK2928_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RK2928_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RK2928_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RK2928_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) RK2928_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RK2928_CLKSEL_CON(7), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK2928_CLKGATE_CON(0), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &rk3036_i2s_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RK2928_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) RK2928_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK2928_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) RK2928_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RK2928_CLKGATE_CON(2), 12, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &rk3036_spdif_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK2928_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) RK2928_CLKGATE_CON(3), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RK2928_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) RK2928_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RK2928_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RK2928_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* aclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* hclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* pclk_cpu gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* aclk_vio gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* xin24m gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* aclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* hclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* pclk_peri gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void __iomem *rk3036_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void rk3036_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (rk3036_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 32, 4, rk3036_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x1f8, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void __init rk3036_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Make uart_pll_clk a child of the gpll, as all other sources are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * not that usable / stable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg_base + RK2928_CLKSEL_CON(13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pr_warn("%s: could not register clock usb480m: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __func__, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rockchip_clk_register_plls(ctx, rk3036_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ARRAY_SIZE(rk3036_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RK3036_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rockchip_clk_register_branches(ctx, rk3036_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ARRAY_SIZE(rk3036_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 2, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &rk3036_cpuclk_data, rk3036_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ARRAY_SIZE(rk3036_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!rk_dump_cru) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rk3036_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rk_dump_cru = rk3036_dump_cru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int __init clk_rk3036_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rk3036_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct of_device_id clk_rk3036_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .compatible = "rockchip,rk3036-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DEVICE_TABLE(of, clk_rk3036_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct platform_driver clk_rk3036_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .name = "clk-rk3036",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .of_match_table = clk_rk3036_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) builtin_platform_driver_probe(clk_rk3036_driver, clk_rk3036_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DESCRIPTION("Rockchip RK3036 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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