^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/rk1808-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK1808_GRF_SOC_STATUS0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK1808_PMUGRF_SOC_CON0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK1808_UART_FRAC_MAX_PRATE 800000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK1808_PDM_FRAC_MAX_PRATE 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK1808_I2S_FRAC_MAX_PRATE 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK1808_VOP_RAW_FRAC_MAX_PRATE 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RK1808_VOP_LITE_FRAC_MAX_PRATE 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum rk1808_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) apll, dpll, cpll, gpll, npll, ppll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct rockchip_pll_rate_table rk1808_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1100000000, 2, 275, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(800000000, 1, 100, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(700000000, 1, 175, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(416000000, 1, 52, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(200000000, 1, 200, 6, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK1808_DIV_ACLKM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK1808_DIV_ACLKM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK1808_DIV_PCLK_DBG_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK1808_DIV_PCLK_DBG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK1808_CLKSEL0(_aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .reg = RK1808_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .val = HIWORD_UPDATE(_aclk_core, RK1808_DIV_ACLKM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) RK1808_DIV_ACLKM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HIWORD_UPDATE(_pclk_dbg, RK1808_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RK1808_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RK1808_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RK1808_CLKSEL0(_aclk_core, _pclk_dbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct rockchip_cpuclk_rate_table rk1808_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RK1808_CPUCLK_RATE(1608000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RK1808_CPUCLK_RATE(1512000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RK1808_CPUCLK_RATE(1488000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RK1808_CPUCLK_RATE(1416000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RK1808_CPUCLK_RATE(1392000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RK1808_CPUCLK_RATE(1296000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RK1808_CPUCLK_RATE(1200000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RK1808_CPUCLK_RATE(1104000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RK1808_CPUCLK_RATE(1008000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RK1808_CPUCLK_RATE(912000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RK1808_CPUCLK_RATE(816000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RK1808_CPUCLK_RATE(696000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) RK1808_CPUCLK_RATE(600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RK1808_CPUCLK_RATE(408000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RK1808_CPUCLK_RATE(312000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RK1808_CPUCLK_RATE(216000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RK1808_CPUCLK_RATE(96000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct rockchip_cpuclk_reg_data rk1808_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .core_reg[0] = RK1808_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .div_core_mask[0] = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .mux_core_alt = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .mux_core_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .mux_core_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PNAME(mux_pll_p) = { "xin24m", "xin32k"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PNAME(mux_gpll_cpll_apll_p) = { "gpll", "cpll", "apll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PNAME(mux_npu_p) = { "clk_npu_div", "clk_npu_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(mux_ddr_p) = { "dpll_ddr", "gpll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PNAME(mux_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PNAME(mux_gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PNAME(mux_dclk_vopraw_p) = { "dclk_vopraw_src", "dclk_vopraw_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PNAME(mux_dclk_voplite_p) = { "dclk_voplite_src", "dclk_voplite_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PNAME(mux_24m_npll_gpll_usb480m_p) = { "xin24m", "npll", "gpll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PNAME(mux_usb3_otg0_suspend_p) = { "xin32k", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PNAME(mux_pcie_aux_p) = { "xin24m", "clk_pcie_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PNAME(mux_gpll_cpll_npll_24m_p) = { "gpll", "cpll", "npll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PNAME(mux_cpll_npll_ppll_p) = { "cpll", "npll", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_gmac_rgmii_speed_p) = { "clk_gmac_tx_src", "clk_gmac_tx_src", "clk_gmac_tx_div50", "clk_gmac_tx_div5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PNAME(mux_gmac_rmii_speed_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_gmac_rx_tx_p) = { "clk_gmac_rgmii_speed", "clk_gmac_rmii_speed" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_gpll_usb480m_cpll_npll_p) = { "gpll", "usb480m", "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PNAME(mux_uart6_p) = { "clk_uart6_src", "clk_uart6_np5", "clk_uart6_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PNAME(mux_uart7_p) = { "clk_uart7_src", "clk_uart7_np5", "clk_uart7_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PNAME(mux_gpll_xin24m_cpll_npll_p) = { "gpll", "xin24m", "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m", "clk_i2s0_8ch_rx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PNAME(mux_i2s0_8ch_rx_out_p) = { "clk_i2s0_8ch_rx", "xin12m", "clk_i2s0_8ch_tx" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PNAME(mux_gpll_usb480m_cpll_ppll_p) = { "gpll", "usb480m", "cpll", "ppll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mux_pciephy_ref_p) = { "xin24m", "clk_pciephy_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(mux_ppll_xin24m_p) = { "ppll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PNAME(mux_xin24m_32k_p) = { "xin24m", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mux_clk_32k_ioe_p) = { "clk_rtc32k_pmu", "xin32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct rockchip_pll_clock rk1808_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0, RK1808_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) RK1808_MODE_CON, 0, 0, 0, rk1808_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0, RK1808_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RK1808_MODE_CON, 2, 1, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0, RK1808_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) RK1808_MODE_CON, 4, 2, 0, rk1808_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0, RK1808_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [npll] = PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0, RK1808_PLL_CON(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) RK1808_MODE_CON, 8, 5, 0, rk1808_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [ppll] = PLL(pll_rk3036, PLL_PPLL, "ppll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0, RK1808_PMU_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RK1808_PMU_MODE_CON, 0, 4, 0, rk1808_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct rockchip_clk_branch rk1808_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct rockchip_clk_branch rk1808_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct rockchip_clk_branch rk1808_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct rockchip_clk_branch rk1808_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct rockchip_clk_branch rk1808_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct rockchip_clk_branch rk1808_uart6_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct rockchip_clk_branch rk1808_uart7_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct rockchip_clk_branch rk1808_dclk_vopraw_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct rockchip_clk_branch rk1808_dclk_voplite_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct rockchip_clk_branch rk1808_pdm_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) RK1808_CLKSEL_CON(30), 15, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct rockchip_clk_branch rk1808_i2s0_8ch_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) RK1808_CLKSEL_CON(32), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct rockchip_clk_branch rk1808_i2s0_8ch_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) RK1808_CLKSEL_CON(34), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct rockchip_clk_branch rk1808_i2s1_2ch_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) RK1808_CLKSEL_CON(36), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct rockchip_clk_branch rk1808_rtc32k_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) RK1808_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct rockchip_clk_branch rk1808_uart0_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) RK1808_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) RK1808_MODE_CON, 10, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RK1808_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GATE(0, "cpll_core", "cpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RK1808_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) RK1808_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RK1808_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) RK1808_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) RK1808_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RK1808_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) RK1808_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) RK1808_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RK1808_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) RK1808_CLKSEL_CON(15), 11, 1, MFLAGS, 12, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) RK1808_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) RK1808_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) RK1808_CLKGATE_CON(1), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GATE(0, "aclk_core2gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RK1808_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) GATE(0, "aclk_gic2core", "aclk_gic_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) RK1808_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) GATE(0, "aclk_spinlock", "aclk_gic_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) RK1808_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RK1808_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RK1808_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) RK1808_CLKSEL_CON(16), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RK1808_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RK1808_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RK1808_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RK1808_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) RK1808_CLKGATE_CON(8), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FACTOR(0, "clk_npu_scan", "clk_npu_pre", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) GATE(SCLK_NPU, "clk_npu", "clk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RK1808_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) COMPOSITE(0, "aclk_npu_pre", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) RK1808_CLKSEL_CON(2), 14, 1, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RK1808_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) COMPOSITE(0, "hclk_npu_pre", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) RK1808_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RK1808_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RK1808_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RK1808_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) COMPOSITE_NOMUX(0, "aclk_npu2mem", "aclk_npu_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RK1808_CLKSEL_CON(2), 4, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RK1808_CLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) RK1808_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) RK1808_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) RK1808_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) RK1808_CLKSEL_CON(17), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) RK1808_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) GATE(ACLK_IMEM0, "aclk_imem0", "aclk_imem_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) RK1808_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) RK1808_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GATE(ACLK_IMEM1, "aclk_imem1", "aclk_imem_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) RK1808_CLKGATE_CON(7), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) RK1808_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) GATE(ACLK_IMEM2, "aclk_imem2", "aclk_imem_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) RK1808_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) RK1808_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GATE(ACLK_IMEM3, "aclk_imem3", "aclk_imem_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RK1808_CLKGATE_CON(7), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RK1808_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) RK1808_CLKSEL_CON(17), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) RK1808_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) RK1808_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) RK1808_CLKGATE_CON(2), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GATE(0, "aclk_split", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) RK1808_CLKGATE_CON(2), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RK1808_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GATE(0, "clk_ddrdfi_ctl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) RK1808_CLKGATE_CON(2), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GATE(0, "clk_stdby", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) RK1808_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GATE(0, "aclk_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) RK1808_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GATE(0, "clk_core_ddrc", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RK1808_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) RK1808_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RK1808_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RK1808_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FACTOR(0, "clk_ddrphy1x_out", "sclk_ddrc", CLK_IGNORE_UNUSED, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) RK1808_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RK1808_CLKGATE_CON(2), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) RK1808_CLKGATE_CON(2), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GATE(PCLK_MSCH, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RK1808_CLKGATE_CON(2), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GATE(PCLK_STDBY, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RK1808_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) RK1808_CLKGATE_CON(2), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GATE(0, "pclk_ddrdfi_ctl", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) RK1808_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) COMPOSITE(HSCLK_VIO, "hsclk_vio", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RK1808_CLKSEL_CON(4), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RK1808_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) COMPOSITE_NOMUX(LSCLK_VIO, "lsclk_vio", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RK1808_CLKSEL_CON(4), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RK1808_CLKGATE_CON(3), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GATE(0, "hsclk_vio_niu", "hsclk_vio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RK1808_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GATE(0, "lsclk_vio_niu", "lsclk_vio", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RK1808_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE(ACLK_VOPRAW, "aclk_vopraw", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RK1808_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GATE(HCLK_VOPRAW, "hclk_vopraw", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) RK1808_CLKGATE_CON(4), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE(ACLK_VOPLITE, "aclk_voplite", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RK1808_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GATE(HCLK_VOPLITE, "hclk_voplite", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) RK1808_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GATE(PCLK_DSI_TX, "pclk_dsi_tx", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RK1808_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE(PCLK_CSI_TX, "pclk_csi_tx", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) RK1808_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) GATE(ACLK_RGA, "aclk_rga", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) RK1808_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) GATE(HCLK_RGA, "hclk_rga", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RK1808_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GATE(ACLK_ISP, "aclk_isp", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) RK1808_CLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GATE(HCLK_ISP, "hclk_isp", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RK1808_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) GATE(ACLK_CIF, "aclk_cif", "hsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RK1808_CLKGATE_CON(4), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) GATE(HCLK_CIF, "hclk_cif", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RK1808_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) GATE(PCLK_CSI2HOST, "pclk_csi2host", "lsclk_vio", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RK1808_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) COMPOSITE(0, "dclk_vopraw_src", mux_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) RK1808_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) RK1808_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) COMPOSITE_FRACMUX(0, "dclk_vopraw_frac", "dclk_vopraw_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RK1808_CLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RK1808_CLKGATE_CON(3), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &rk1808_dclk_vopraw_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RK1808_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) COMPOSITE(0, "dclk_voplite_src", mux_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RK1808_CLKSEL_CON(7), 10, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) RK1808_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) COMPOSITE_FRACMUX(0, "dclk_voplite_frac", "dclk_voplite_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) RK1808_CLKSEL_CON(8), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RK1808_CLKGATE_CON(3), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &rk1808_dclk_voplite_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) RK1808_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) COMPOSITE_NOMUX(SCLK_TXESC, "clk_txesc", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) RK1808_CLKSEL_CON(9), 0, 12, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) RK1808_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) COMPOSITE(SCLK_RGA, "clk_rga", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) RK1808_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RK1808_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) RK1808_CLKSEL_CON(10), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RK1808_CLKGATE_CON(3), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) COMPOSITE(DCLK_CIF, "dclk_cif", mux_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) RK1808_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RK1808_CLKGATE_CON(3), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_24m_npll_gpll_usb480m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) RK1808_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) RK1808_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Clock-Architecture Diagram 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* PD_PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) COMPOSITE_NODIV(0, "clk_pcie_src", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) RK1808_CLKSEL_CON(12), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) RK1808_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DIV(HSCLK_PCIE, "hsclk_pcie", "clk_pcie_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) RK1808_CLKSEL_CON(12), 0, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DIV(LSCLK_PCIE, "lsclk_pcie", "clk_pcie_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) RK1808_CLKSEL_CON(12), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(0, "hsclk_pcie_niu", "hsclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) RK1808_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE(0, "lsclk_pcie_niu", "lsclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) RK1808_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GATE(0, "pclk_pcie_grf", "lsclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) RK1808_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GATE(ACLK_USB3OTG, "aclk_usb3otg", "hsclk_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) RK1808_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GATE(HCLK_HOST, "hclk_host", "lsclk_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) RK1808_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GATE(HCLK_HOST_ARB, "hclk_host_arb", "lsclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) RK1808_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) COMPOSITE(ACLK_PCIE, "aclk_pcie", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) RK1808_CLKSEL_CON(15), 8, 1, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RK1808_CLKGATE_CON(5), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DIV(0, "pclk_pcie_pre", "aclk_pcie", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) RK1808_CLKSEL_CON(15), 4, 4, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(0, "aclk_pcie_niu", "aclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) RK1808_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GATE(ACLK_PCIE_MST, "aclk_pcie_mst", "aclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) RK1808_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GATE(ACLK_PCIE_SLV, "aclk_pcie_slv", "aclk_pcie", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RK1808_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GATE(0, "pclk_pcie_niu", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) RK1808_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GATE(0, "pclk_pcie_dbi", "pclk_pcie_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) RK1808_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GATE(PCLK_PCIE, "pclk_pcie", "pclk_pcie_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) RK1808_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) COMPOSITE(0, "clk_pcie_aux_src", mux_cpll_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RK1808_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RK1808_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) COMPOSITE_NODIV(SCLK_PCIE_AUX, "clk_pcie_aux", mux_pcie_aux_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) RK1808_CLKSEL_CON(14), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) RK1808_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GATE(SCLK_USB3_OTG0_REF, "clk_usb3_otg0_ref", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RK1808_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) COMPOSITE(SCLK_USB3_OTG0_SUSPEND, "clk_usb3_otg0_suspend", mux_usb3_otg0_suspend_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) RK1808_CLKSEL_CON(13), 12, 1, MFLAGS, 0, 10, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RK1808_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Clock-Architecture Diagram 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* PD_PHP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) RK1808_CLKSEL_CON(19), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) RK1808_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) RK1808_CLKSEL_CON(19), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) RK1808_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RK1808_CLKSEL_CON(19), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) RK1808_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) RK1808_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) RK1808_CLKGATE_CON(8), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* PD_MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(0, "hclk_mmc_sfc", "msclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) RK1808_CLKGATE_CON(9), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GATE(0, "hclk_mmc_sfc_niu", "hclk_mmc_sfc", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) RK1808_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_sfc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) RK1808_CLKGATE_CON(9), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_sfc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) RK1808_CLKGATE_CON(9), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) RK1808_CLKGATE_CON(9), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) RK1808_CLKSEL_CON(22), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) RK1808_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) RK1808_CLKSEL_CON(23), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) RK1808_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK1808_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK1808_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) RK1808_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) RK1808_CLKSEL_CON(24), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) RK1808_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) RK1808_CLKSEL_CON(25), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) RK1808_CLKGATE_CON(9), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK1808_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK1808_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) RK1808_CLKGATE_CON(9), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) RK1808_CLKSEL_CON(20), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RK1808_CLKGATE_CON(9), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) RK1808_CLKSEL_CON(21), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) RK1808_CLKGATE_CON(9), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK1808_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK1808_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) RK1808_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) RK1808_CLKGATE_CON(9), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* PD_MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GATE(0, "pclk_sd_gmac", "lsclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) RK1808_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) GATE(0, "aclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) RK1808_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GATE(0, "hclk_sd_gmac", "msclk_peri", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) RK1808_CLKGATE_CON(10), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) GATE(0, "pclk_gmac_niu", "pclk_sd_gmac", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) RK1808_CLKGATE_CON(10), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GATE(PCLK_GMAC, "pclk_gmac", "pclk_sd_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) RK1808_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GATE(0, "aclk_gmac_niu", "aclk_sd_gmac", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) RK1808_CLKGATE_CON(10), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GATE(ACLK_GMAC, "aclk_gmac", "aclk_sd_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RK1808_CLKGATE_CON(10), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GATE(0, "hclk_gmac_niu", "hclk_sd_gmac", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) RK1808_CLKGATE_CON(10), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GATE(HCLK_SDIO, "hclk_sdio", "hclk_sd_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) RK1808_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) RK1808_CLKGATE_CON(10), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) COMPOSITE(SCLK_GMAC_OUT, "clk_gmac_out", mux_cpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) RK1808_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RK1808_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_cpll_npll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RK1808_CLKSEL_CON(26), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) RK1808_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RK1808_CLKSEL_CON(27), 0, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GATE(SCLK_GMAC_REF, "clk_gmac_ref", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) RK1808_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GATE(0, "clk_gmac_tx_src", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) RK1808_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GATE(0, "clk_gmac_rx_src", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RK1808_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GATE(SCLK_GMAC_REFOUT, "clk_gmac_refout", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RK1808_CLKGATE_CON(10), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) FACTOR(0, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) FACTOR(0, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) FACTOR(0, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) FACTOR(0, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MUX(SCLK_GMAC_RGMII_SPEED, "clk_gmac_rgmii_speed", mux_gmac_rgmii_speed_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) RK1808_CLKSEL_CON(27), 2, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MUX(SCLK_GMAC_RMII_SPEED, "clk_gmac_rmii_speed", mux_gmac_rmii_speed_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RK1808_CLKSEL_CON(27), 1, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MUX(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", mux_gmac_rx_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) RK1808_CLKSEL_CON(27), 4, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) RK1808_CLKSEL_CON(27), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RK1808_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RK1808_CLKSEL_CON(27), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RK1808_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RK1808_CLKSEL_CON(28), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) RK1808_CLKGATE_CON(11), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) RK1808_CLKSEL_CON(28), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) RK1808_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RK1808_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RK1808_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(0, "msclk_sub", "msclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RK1808_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) GATE(ACLK_DMAC, "aclk_dmac", "msclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RK1808_CLKGATE_CON(14), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GATE(HCLK_ROM, "hclk_rom", "msclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RK1808_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) GATE(ACLK_CRYPTO, "aclk_crypto", "msclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RK1808_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) GATE(HCLK_CRYPTO, "hclk_crypto", "msclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RK1808_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(ACLK_DCF, "aclk_dcf", "msclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) RK1808_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RK1808_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(PCLK_DCF, "pclk_dcf", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RK1808_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(PCLK_UART1, "pclk_uart1", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) RK1808_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(PCLK_UART2, "pclk_uart2", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RK1808_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(PCLK_UART3, "pclk_uart3", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RK1808_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) GATE(PCLK_UART4, "pclk_uart4", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RK1808_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GATE(PCLK_UART5, "pclk_uart5", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RK1808_CLKGATE_CON(15), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GATE(PCLK_UART6, "pclk_uart6", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RK1808_CLKGATE_CON(15), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GATE(PCLK_UART7, "pclk_uart7", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RK1808_CLKGATE_CON(15), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GATE(PCLK_I2C1, "pclk_i2c1", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RK1808_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) GATE(PCLK_I2C2, "pclk_i2c2", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RK1808_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(PCLK_I2C3, "pclk_i2c3", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RK1808_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(PCLK_I2C4, "pclk_i2c4", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RK1808_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GATE(PCLK_I2C5, "pclk_i2c5", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RK1808_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GATE(PCLK_SPI0, "pclk_spi0", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RK1808_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GATE(PCLK_SPI1, "pclk_spi1", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RK1808_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GATE(PCLK_SPI2, "pclk_spi2", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RK1808_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GATE(PCLK_TSADC, "pclk_tsadc", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) RK1808_CLKGATE_CON(16), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GATE(PCLK_SARADC, "pclk_saradc", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) RK1808_CLKGATE_CON(16), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(PCLK_EFUSE, "pclk_efuse", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RK1808_CLKGATE_CON(16), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) RK1808_CLKGATE_CON(16), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(PCLK_GPIO2, "pclk_gpio2", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) RK1808_CLKGATE_CON(16), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(PCLK_GPIO3, "pclk_gpio3", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) RK1808_CLKGATE_CON(16), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GATE(PCLK_GPIO4, "pclk_gpio4", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) RK1808_CLKGATE_CON(16), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RK1808_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GATE(PCLK_PWM1, "pclk_pwm1", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) RK1808_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GATE(PCLK_PWM2, "pclk_pwm2", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) RK1808_CLKGATE_CON(16), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GATE(PCLK_TIMER, "pclk_timer", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) RK1808_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GATE(PCLK_WDT, "pclk_wdt", "lsclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) RK1808_CLKGATE_CON(17), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE(0, "pclk_grf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RK1808_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GATE(0, "pclk_sgrf", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) RK1808_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(0, "hclk_audio_pre", "msclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RK1808_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(0, "pclk_top_pre", "lsclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) RK1808_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) RK1808_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) RK1808_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) RK1808_CLKSEL_CON(29), 15, 1, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RK1808_CLKGATE_CON(11), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COMPOSITE(0, "clk_uart1_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RK1808_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) RK1808_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RK1808_CLKSEL_CON(39), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) RK1808_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) RK1808_CLKSEL_CON(40), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) RK1808_CLKGATE_CON(11), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &rk1808_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RK1808_CLKGATE_CON(11), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) COMPOSITE(0, "clk_uart2_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) RK1808_CLKSEL_CON(41), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) RK1808_CLKGATE_CON(11), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RK1808_CLKSEL_CON(42), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) RK1808_CLKGATE_CON(11), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RK1808_CLKSEL_CON(43), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) RK1808_CLKGATE_CON(11), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &rk1808_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RK1808_CLKGATE_CON(11), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) COMPOSITE(0, "clk_uart3_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) RK1808_CLKSEL_CON(44), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RK1808_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RK1808_CLKSEL_CON(45), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RK1808_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RK1808_CLKSEL_CON(46), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RK1808_CLKGATE_CON(12), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &rk1808_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) RK1808_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) COMPOSITE(0, "clk_uart4_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) RK1808_CLKSEL_CON(47), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) RK1808_CLKGATE_CON(12), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RK1808_CLKSEL_CON(48), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) RK1808_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) RK1808_CLKSEL_CON(49), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) RK1808_CLKGATE_CON(12), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &rk1808_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) RK1808_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) COMPOSITE(0, "clk_uart5_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) RK1808_CLKSEL_CON(50), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) RK1808_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RK1808_CLKSEL_CON(51), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RK1808_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) RK1808_CLKSEL_CON(52), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RK1808_CLKGATE_CON(12), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &rk1808_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) RK1808_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) COMPOSITE(0, "clk_uart6_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) RK1808_CLKSEL_CON(53), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) RK1808_CLKGATE_CON(12), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart6_np5", "clk_uart6_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) RK1808_CLKSEL_CON(54), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RK1808_CLKGATE_CON(12), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) COMPOSITE_FRACMUX(0, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) RK1808_CLKSEL_CON(55), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) RK1808_CLKGATE_CON(12), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &rk1808_uart6_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) RK1808_CLKGATE_CON(12), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) COMPOSITE(0, "clk_uart7_src", mux_gpll_usb480m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) RK1808_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) RK1808_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart7_np5", "clk_uart7_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) RK1808_CLKSEL_CON(57), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) RK1808_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) COMPOSITE_FRACMUX(0, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) RK1808_CLKSEL_CON(58), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) RK1808_CLKGATE_CON(13), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &rk1808_uart7_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) RK1808_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) RK1808_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) RK1808_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) RK1808_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) RK1808_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) RK1808_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) RK1808_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) RK1808_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) RK1808_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) RK1808_CLKSEL_CON(71), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) RK1808_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) RK1808_CLKGATE_CON(13), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) RK1808_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) RK1808_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) RK1808_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) RK1808_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) RK1808_CLKSEL_CON(62), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) RK1808_CLKGATE_CON(13), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) RK1808_CLKSEL_CON(63), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) RK1808_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) COMPOSITE(SCLK_EFUSE_S, "clk_efuse_s", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RK1808_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) RK1808_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) COMPOSITE(SCLK_EFUSE_NS, "clk_efuse_ns", mux_gpll_cpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) RK1808_CLKSEL_CON(64), 14, 2, MFLAGS, 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) RK1808_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RK1808_CLKSEL_CON(65), 15, 1, MFLAGS, 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) RK1808_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) RK1808_CLKSEL_CON(66), 15, 1, MFLAGS, 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RK1808_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RK1808_CLKSEL_CON(67), 15, 1, MFLAGS, 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) RK1808_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) RK1808_CLKSEL_CON(68), 15, 1, MFLAGS, 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RK1808_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RK1808_CLKSEL_CON(69), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RK1808_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) RK1808_CLKSEL_CON(69), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) RK1808_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) RK1808_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RK1808_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RK1808_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) RK1808_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK1808_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RK1808_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RK1808_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RK1808_CLKGATE_CON(14), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Clock-Architecture Diagram 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* PD_AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GATE(0, "hclk_audio_niu", "hclk_audio_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RK1808_CLKGATE_CON(18), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GATE(HCLK_VAD, "hclk_vad", "hclk_audio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RK1808_CLKGATE_CON(18), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GATE(HCLK_PDM, "hclk_pdm", "hclk_audio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) RK1808_CLKGATE_CON(18), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RK1808_CLKGATE_CON(18), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RK1808_CLKGATE_CON(18), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RK1808_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RK1808_CLKGATE_CON(17), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RK1808_CLKSEL_CON(31), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RK1808_CLKGATE_CON(17), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) &rk1808_pdm_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RK1808_CLKGATE_CON(17), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) RK1808_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK1808_CLKGATE_CON(17), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) RK1808_CLKSEL_CON(33), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) RK1808_CLKGATE_CON(17), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) &rk1808_i2s0_8ch_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RK1808_CLKSEL_CON(32), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RK1808_CLKGATE_CON(17), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK1808_CLKSEL_CON(32), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) RK1808_CLKGATE_CON(17), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RK1808_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RK1808_CLKGATE_CON(18), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RK1808_CLKSEL_CON(35), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RK1808_CLKGATE_CON(18), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) &rk1808_i2s0_8ch_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RK1808_CLKSEL_CON(34), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RK1808_CLKGATE_CON(18), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) COMPOSITE_NODIV(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", mux_i2s0_8ch_rx_out_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RK1808_CLKSEL_CON(34), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) RK1808_CLKGATE_CON(18), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) RK1808_CLKSEL_CON(36), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) RK1808_CLKGATE_CON(18), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) RK1808_CLKSEL_CON(37), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) RK1808_CLKGATE_CON(18), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) &rk1808_i2s1_2ch_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) RK1808_CLKGATE_CON(18), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) RK1808_CLKSEL_CON(36), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) RK1808_CLKGATE_CON(18), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Clock-Architecture Diagram 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, RK1808_CLKGATE_CON(19), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GATE(0, "pclk_usb3_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GATE(0, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, RK1808_CLKGATE_CON(19), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Clock-Architecture Diagram 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* PD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) COMPOSITE_FRACMUX(SCLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) RK1808_PMU_CLKSEL_CON(1), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) RK1808_PMU_CLKGATE_CON(0), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) &rk1808_rtc32k_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) RK1808_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) RK1808_PMU_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) RK1808_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) RK1808_PMU_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) RK1808_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) RK1808_PMU_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) COMPOSITE(0, "clk_uart0_pmu_src", mux_gpll_usb480m_cpll_ppll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) RK1808_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) RK1808_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) RK1808_PMU_CLKSEL_CON(4), 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) RK1808_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) RK1808_PMU_CLKSEL_CON(5), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) &rk1808_uart0_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) RK1808_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) RK1808_PMU_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) COMPOSITE(SCLK_PMU_I2C0, "clk_pmu_i2c0", mux_ppll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) RK1808_PMU_CLKSEL_CON(7), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) RK1808_PMU_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) COMPOSITE(DBCLK_PMU_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) RK1808_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) RK1808_PMU_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "ppll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) RK1808_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) RK1808_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) RK1808_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RK1808_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) RK1808_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) RK1808_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) FACTOR(0, "clk_ppll_ph0", "ppll", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) COMPOSITE_NOMUX(0, "clk_pciephy_src", "clk_ppll_ph0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) RK1808_PMU_CLKSEL_CON(7), 0, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RK1808_PMU_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) COMPOSITE_NODIV(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pciephy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) RK1808_PMU_CLKSEL_CON(7), 4, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) RK1808_PMU_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) RK1808_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) RK1808_PMU_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_pre", 0, RK1808_PMU_CLKGATE_CON(0), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static void __iomem *rk1808_cru_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) void rk1808_dump_cru(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (rk1808_cru_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pr_warn("CRU:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) 32, 4, rk1808_cru_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) 0x500, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 32, 4, rk1808_cru_base + 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 0x100, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) EXPORT_SYMBOL_GPL(rk1808_dump_cru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int rk1808_clk_panic(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) unsigned long ev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) rk1808_dump_cru();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static struct notifier_block rk1808_clk_panic_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .notifier_call = rk1808_clk_panic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static void __init rk1808_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) rk1808_cru_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) clks = ctx->clk_data.clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) rockchip_clk_register_plls(ctx, rk1808_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ARRAY_SIZE(rk1808_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) RK1808_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) rockchip_clk_register_branches(ctx, rk1808_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ARRAY_SIZE(rk1808_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) 3, clks[PLL_APLL], clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) &rk1808_cpuclk_data, rk1808_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ARRAY_SIZE(rk1808_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) rockchip_register_softrst(np, 16, reg_base + RK1808_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) rockchip_register_restart_notifier(ctx, RK1808_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) &rk1808_clk_panic_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) CLK_OF_DECLARE(rk1808_cru, "rockchip,rk1808-cru", rk1808_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int __init clk_rk1808_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) rk1808_clk_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const struct of_device_id clk_rk1808_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .compatible = "rockchip,rk1808-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) MODULE_DEVICE_TABLE(of, clk_rk1808_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static struct platform_driver clk_rk1808_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .name = "clk-rk1808",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .of_match_table = clk_rk1808_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) builtin_platform_driver_probe(clk_rk1808_driver, clk_rk1808_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) MODULE_DESCRIPTION("Rockchip RK1808 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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