^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Elaine Zhang<zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/px30-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PX30_GRF_SOC_STATUS0 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum px30_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) apll, dpll, cpll, npll, apll_b_h, apll_b_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum px30_pmu_plls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) gpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct rockchip_pll_rate_table px30_pll_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PX30_DIV_ACLKM_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PX30_DIV_ACLKM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PX30_DIV_PCLK_DBG_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PX30_DIV_PCLK_DBG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg = PX30_CLKSEL_CON(0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PX30_DIV_ACLKM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PX30_DIV_PCLK_DBG_SHIFT), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .prate = _prate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .divs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PX30_CLKSEL0(_aclk_core, _pclk_dbg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PX30_CPUCLK_RATE(1608000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PX30_CPUCLK_RATE(1584000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PX30_CPUCLK_RATE(1560000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PX30_CPUCLK_RATE(1536000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PX30_CPUCLK_RATE(1512000000, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PX30_CPUCLK_RATE(1488000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PX30_CPUCLK_RATE(1464000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PX30_CPUCLK_RATE(1440000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PX30_CPUCLK_RATE(1416000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PX30_CPUCLK_RATE(1392000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PX30_CPUCLK_RATE(1368000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PX30_CPUCLK_RATE(1344000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PX30_CPUCLK_RATE(1320000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PX30_CPUCLK_RATE(1296000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PX30_CPUCLK_RATE(1272000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PX30_CPUCLK_RATE(1248000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PX30_CPUCLK_RATE(1224000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PX30_CPUCLK_RATE(1200000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PX30_CPUCLK_RATE(1104000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PX30_CPUCLK_RATE(1008000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PX30_CPUCLK_RATE(912000000, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PX30_CPUCLK_RATE(816000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PX30_CPUCLK_RATE(696000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PX30_CPUCLK_RATE(600000000, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PX30_CPUCLK_RATE(408000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PX30_CPUCLK_RATE(312000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PX30_CPUCLK_RATE(216000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PX30_CPUCLK_RATE(96000000, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .core_reg[0] = PX30_CLKSEL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .div_core_shift[0] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .div_core_mask[0] = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .num_cores = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mux_core_alt = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .mux_core_main = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mux_core_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mux_core_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .pll_name = "pll_apll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PNAME(mux_pll_p) = { "xin24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PNAME(mux_gpll_dmycpll_usb480m_npll_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PNAME(mux_gpll_dmycpll_usb480m_dmynpll_p) = { "gpll", "dummy_cpll", "usb480m", "dummy_npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PNAME(mux_gpll_npll_p) = { "gpll", "dummy_npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "dummy_npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "dummy_npll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "dummy_npll", "usb480m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0, PX30_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0, PX30_PLL_CON(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PX30_MODE_CON, 4, 1, 0, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0, PX30_PLL_CON(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK_IS_CRITICAL, PX30_PLL_CON(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MFLAGS CLK_MUX_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DFLAGS CLK_DIVIDER_HIWORD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Clock-Architecture Diagram 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PX30_MODE_CON, 8, 2, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Clock-Architecture Diagram 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* PD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PX30_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PX30_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PX30_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PX30_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PX30_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PX30_CLKGATE_CON(17), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PX30_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PX30_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PX30_CLKGATE_CON(17), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PX30_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PX30_CLKGATE_CON(17), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* PD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GATE(SCLK_GPU, "clk_gpu", "clk_gpu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PX30_CLKGATE_CON(0), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PX30_CLKGATE_CON(17), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PX30_CLKGATE_CON(0), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PX30_CLKGATE_CON(17), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PX30_CLKGATE_CON(17), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Clock-Architecture Diagram 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* PD_DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PX30_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PX30_CLKGATE_CON(0), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ROCKCHIP_DDRCLK_SIP_V2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PX30_CLKGATE_CON(1), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PX30_CLKGATE_CON(1), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PX30_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PX30_CLKGATE_CON(1), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PX30_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PX30_CLKGATE_CON(1), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PX30_CLKGATE_CON(1), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PX30_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PX30_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PX30_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PX30_CLKGATE_CON(1), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PX30_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PX30_CLKGATE_CON(1), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PX30_CLKGATE_CON(1), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PX30_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Clock-Architecture Diagram 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PX30_CLKGATE_CON(4), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PX30_CLKGATE_CON(4), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PX30_CLKGATE_CON(4), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PX30_CLKGATE_CON(4), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PX30_CLKGATE_CON(4), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PX30_CLKGATE_CON(4), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Clock-Architecture Diagram 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PX30_CLKGATE_CON(2), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PX30_CLKGATE_CON(2), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PX30_CLKGATE_CON(2), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PX30_CLKGATE_CON(2), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PX30_CLKGATE_CON(2), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PX30_CLKGATE_CON(2), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PX30_CLKSEL_CON(6), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PX30_CLKGATE_CON(2), 3, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &px30_dclk_vopb_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PX30_CLKGATE_CON(2), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PX30_CLKGATE_CON(2), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PX30_CLKSEL_CON(9), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PX30_CLKGATE_CON(2), 7, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &px30_dclk_vopl_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PX30_CLKGATE_CON(2), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* PD_VPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PX30_CLKGATE_CON(4), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PX30_CLKGATE_CON(4), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PX30_CLKGATE_CON(4), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Clock-Architecture Diagram 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PX30_CLKGATE_CON(5), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PX30_CLKGATE_CON(5), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* PD_MMC_NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PX30_CLKGATE_CON(6), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PX30_CLKGATE_CON(5), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PX30_CLKGATE_CON(5), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PX30_CLKGATE_CON(5), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PX30_CLKGATE_CON(6), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PX30_CLKGATE_CON(6), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PX30_CLKGATE_CON(6), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PX30_CLKGATE_CON(6), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PX30_CLKGATE_CON(6), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PX30_CLKGATE_CON(6), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PX30_CLKGATE_CON(6), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PX30_SDMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PX30_SDMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PX30_SDIO_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PX30_SDIO_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PX30_EMMC_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PX30_EMMC_CON1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* PD_SDCARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PX30_CLKGATE_CON(6), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PX30_CLKGATE_CON(6), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PX30_CLKGATE_CON(6), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PX30_CLKGATE_CON(6), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* PD_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PX30_CLKGATE_CON(7), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PX30_CLKGATE_CON(7), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PX30_CLKGATE_CON(7), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PX30_CLKGATE_CON(7), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PX30_CLKGATE_CON(7), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PX30_CLKGATE_CON(7), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PX30_CLKGATE_CON(7), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PX30_CLKGATE_CON(8), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Clock-Architecture Diagram 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PX30_CLKGATE_CON(8), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PX30_CLKGATE_CON(8), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PX30_CLKGATE_CON(8), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PX30_CLKGATE_CON(8), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PX30_CLKGATE_CON(8), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PX30_CLKGATE_CON(9), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PX30_CLKSEL_CON(27), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PX30_CLKGATE_CON(9), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &px30_pdm_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PX30_CLKGATE_CON(9), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PX30_CLKGATE_CON(9), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PX30_CLKSEL_CON(29), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PX30_CLKGATE_CON(9), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &px30_i2s0_tx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PX30_CLKGATE_CON(9), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PX30_CLKGATE_CON(9), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PX30_CLKGATE_CON(17), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PX30_CLKSEL_CON(59), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PX30_CLKGATE_CON(17), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &px30_i2s0_rx_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PX30_CLKGATE_CON(17), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PX30_CLKGATE_CON(17), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PX30_CLKGATE_CON(10), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PX30_CLKSEL_CON(31), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PX30_CLKGATE_CON(10), 1, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &px30_i2s1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PX30_CLKGATE_CON(10), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PX30_CLKGATE_CON(10), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PX30_CLKGATE_CON(10), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PX30_CLKSEL_CON(33), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PX30_CLKGATE_CON(10), 5, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) &px30_i2s2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PX30_CLKGATE_CON(10), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PX30_CLKGATE_CON(10), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PX30_CLKGATE_CON(10), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PX30_CLKGATE_CON(10), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PX30_CLKSEL_CON(36), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PX30_CLKGATE_CON(10), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &px30_uart1_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PX30_CLKGATE_CON(10), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PX30_CLKGATE_CON(11), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PX30_CLKGATE_CON(11), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PX30_CLKSEL_CON(39), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PX30_CLKGATE_CON(11), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &px30_uart2_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PX30_CLKGATE_CON(11), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PX30_CLKGATE_CON(11), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PX30_CLKGATE_CON(11), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PX30_CLKSEL_CON(42), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PX30_CLKGATE_CON(11), 6, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &px30_uart3_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PX30_CLKGATE_CON(11), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PX30_CLKGATE_CON(11), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PX30_CLKGATE_CON(11), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PX30_CLKSEL_CON(45), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PX30_CLKGATE_CON(11), 10, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) &px30_uart4_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PX30_CLKGATE_CON(11), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PX30_CLKGATE_CON(11), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PX30_CLKGATE_CON(11), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PX30_CLKSEL_CON(48), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PX30_CLKGATE_CON(11), 14, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &px30_uart5_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PX30_CLKGATE_CON(11), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PX30_CLKGATE_CON(12), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PX30_CLKGATE_CON(12), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PX30_CLKGATE_CON(12), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PX30_CLKGATE_CON(12), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PX30_CLKGATE_CON(12), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PX30_CLKGATE_CON(12), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PX30_CLKGATE_CON(12), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PX30_CLKGATE_CON(12), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PX30_CLKGATE_CON(13), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PX30_CLKGATE_CON(13), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PX30_CLKGATE_CON(13), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PX30_CLKGATE_CON(13), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PX30_CLKGATE_CON(13), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PX30_CLKGATE_CON(13), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PX30_CLKGATE_CON(12), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PX30_CLKGATE_CON(12), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PX30_CLKGATE_CON(12), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* PD_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PX30_CLKGATE_CON(8), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PX30_CLKGATE_CON(8), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PX30_CLKGATE_CON(8), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PX30_CLKGATE_CON(8), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* PD_BUS_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(16), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* PD_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(4), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* PD_VO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* PD_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* aclk_dmac is controlled by sgrf_soc_con1[11]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(14), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* PD_VPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* PD_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* PD_SDCARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* PD_PERI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* PD_MMC_NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* PD_USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IS_CRITICAL, PX30_CLKGATE_CON(7), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* PD_GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PX30_CLKGATE_CON(8), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PX30_CLKGATE_CON(8), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PX30_CLKGATE_CON(8), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PX30_CLKGATE_CON(8), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct rockchip_clk_branch px30_gpu_src_clk[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_dmynpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PX30_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct rockchip_clk_branch rk3326_gpu_src_clk[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) COMPOSITE(0, "clk_gpu_src", mux_gpll_dmycpll_usb480m_npll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PX30_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Clock-Architecture Diagram 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PX30_PMU_CLKSEL_CON(1), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &px30_rtc32k_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PX30_PMU_CLKSEL_CON(5), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &px30_uart0_pmu_fracmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * Clock-Architecture Diagram 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* PD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static struct rockchip_clk_branch px30_clk_ddrphy_otp[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PX30_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) CLK_IGNORE_UNUSED, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PX30_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PX30_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PX30_CLKGATE_CON(13), 6, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct rockchip_clk_branch px30s_clk_ddrphy_otp[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) COMPOSITE(0, "clk_ddrphy1x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PX30_CLKGATE_CON(0), 14, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy1x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) CLK_IGNORE_UNUSED, 1, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PX30_CLKGATE_CON(1), 0, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) COMPOSITE(SCLK_OTP_USR, "clk_otp_usr", mux_xin24m_gpll_p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PX30_CLKSEL_CON(56), 8, 1, MFLAGS, 0, 8, DFLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PX30_CLKGATE_CON(12), 11, GFLAGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static __initdata struct rockchip_clk_provider *cru_ctx, *pmucru_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void __init px30_register_armclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cru_ctx->clk_data.clks[PLL_APLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pmucru_ctx->clk_data.clks[PLL_GPLL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) &px30_cpuclk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) px30_cpuclk_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ARRAY_SIZE(px30_cpuclk_rates));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void __init px30_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pr_err("%s: could not map cru region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pr_err("%s: rockchip clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cru_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rockchip_clk_register_plls(ctx, px30_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ARRAY_SIZE(px30_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PX30_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (pmucru_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) px30_register_armclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) rockchip_clk_register_branches(ctx, px30_clk_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ARRAY_SIZE(px30_clk_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (of_machine_is_compatible("rockchip,px30"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) rockchip_clk_register_branches(ctx, px30_gpu_src_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ARRAY_SIZE(px30_gpu_src_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ARRAY_SIZE(rk3326_gpu_src_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rockchip_soc_id_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (soc_is_px30s())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) rockchip_clk_register_branches(ctx, px30s_clk_ddrphy_otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ARRAY_SIZE(px30s_clk_ddrphy_otp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) rockchip_clk_register_branches(ctx, px30_clk_ddrphy_otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ARRAY_SIZE(px30_clk_ddrphy_otp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ROCKCHIP_SOFTRST_HIWORD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void __init px30_pmu_clk_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct rockchip_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pr_err("%s: could not map cru pmu region\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (IS_ERR(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pr_err("%s: rockchip pmu clk init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pmucru_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (cru_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) px30_register_armclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ARRAY_SIZE(px30_clk_pmu_branches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) rockchip_clk_of_add_provider(np, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct clk_px30_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) void (*inits)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct clk_px30_inits clk_px30_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .inits = px30_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct clk_px30_inits clk_px30_pmu_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .inits = px30_pmu_clk_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct of_device_id clk_px30_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .compatible = "rockchip,px30-cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .data = &clk_px30_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .compatible = "rockchip,px30-pmucru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .data = &clk_px30_pmu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MODULE_DEVICE_TABLE(of, clk_px30_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int __init clk_px30_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) const struct clk_px30_inits *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) match = of_match_device(clk_px30_match_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) init_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (init_data->inits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) init_data->inits(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static struct platform_driver clk_px30_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = "clk-px30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .of_match_table = clk_px30_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) builtin_platform_driver_probe(clk_px30_driver, clk_px30_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MODULE_DESCRIPTION("Rockchip PX30 Clock Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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