Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct rockchip_muxgrf_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	struct clk_hw		hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	struct regmap		*regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	u32			reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	u32			shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u32			width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	int			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	unsigned int mask = GENMASK(mux->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	regmap_read(mux->regmap, mux->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	val >>= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	val = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	val <<= mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	if (mux->flags & CLK_MUX_HIWORD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		return regmap_update_bits(mux->regmap, mux->reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct clk_ops rockchip_muxgrf_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.get_parent = rockchip_muxgrf_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.set_parent = rockchip_muxgrf_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *rockchip_clk_register_muxgrf(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				const char *const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 				int flags, struct regmap *regmap, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				int shift, int width, int mux_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct rockchip_muxgrf_clock *muxgrf_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		pr_err("%s: regmap not available\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	if (!muxgrf_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	init.ops = &rockchip_muxgrf_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	muxgrf_clock->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	muxgrf_clock->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	muxgrf_clock->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	muxgrf_clock->shift = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	muxgrf_clock->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	muxgrf_clock->flags = mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	clk = clk_register(NULL, &muxgrf_clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 		kfree(muxgrf_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }