Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2021 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pm_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) struct rockchip_link_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	const char *pname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct rockchip_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	const struct rockchip_link_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct rockchip_link_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	const char *pname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	const char *link_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	const struct rockchip_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GATE_LINK(_name, _pname, _shift)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.name = _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.pname = _pname,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.shift = (_shift),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int register_clocks(struct rockchip_link_clk *priv, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	gate = devm_kzalloc(dev, sizeof(struct clk_gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	init.name = priv->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	init.ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	init.flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	init.parent_names = &priv->pname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* struct clk_gate assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	gate->reg = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	gate->bit_idx = priv->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	gate->flags = GFLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	gate->lock = &priv->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	clk = devm_clk_register(dev, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const struct rockchip_link_info rk3588_clk_gate_link_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	GATE_LINK("aclk_isp1_pre", "aclk_isp1_root", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	GATE_LINK("hclk_isp1_pre", "hclk_isp1_root", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	GATE_LINK("hclk_nvm", "hclk_nvm_root", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	GATE_LINK("aclk_usb", "aclk_usb_root", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	GATE_LINK("hclk_usb", "hclk_usb_root", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	GATE_LINK("aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	GATE_LINK("aclk_vdpu_low_pre", "aclk_vdpu_low_root", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	GATE_LINK("aclk_rkvenc1_pre", "aclk_rkvenc1_root", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	GATE_LINK("hclk_rkvenc1_pre", "hclk_rkvenc1_root", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	GATE_LINK("hclk_rkvdec0_pre", "hclk_rkvdec0_root", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	GATE_LINK("aclk_rkvdec0_pre", "aclk_rkvdec0_root", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GATE_LINK("hclk_rkvdec1_pre", "hclk_rkvdec1_root", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	GATE_LINK("aclk_rkvdec1_pre", "aclk_rkvdec1_root", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	GATE_LINK("aclk_hdcp0_pre", "aclk_vo0_root", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	GATE_LINK("hclk_vo0", "hclk_vo0_root", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	GATE_LINK("aclk_hdcp1_pre", "aclk_hdcp1_root", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	GATE_LINK("hclk_vo1", "hclk_vo1_root", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	GATE_LINK("aclk_av1_pre", "aclk_av1_root", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	GATE_LINK("pclk_av1_pre", "pclk_av1_root", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	GATE_LINK("hclk_sdio_pre", "hclk_sdio_root", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	GATE_LINK("pclk_vo0_grf", "pclk_vo0_root", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	GATE_LINK("pclk_vo1_grf", "pclk_vo1_root", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct rockchip_link rk3588_clk_gate_link = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.num = ARRAY_SIZE(rk3588_clk_gate_link_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.info = rk3588_clk_gate_link_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct of_device_id rockchip_clk_link_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.compatible = "rockchip,rk3588-clock-gate-link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.data = (void *)&rk3588_clk_gate_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MODULE_DEVICE_TABLE(of, rockchip_clk_link_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct rockchip_link_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rockchip_get_link_infos(const struct rockchip_link *link, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	const struct rockchip_link_info *info = link->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	for (i = 0; i < link->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (strcmp(info->name, name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		info++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int rockchip_clk_link_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct rockchip_link_clk *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	const struct rockchip_link_info *link_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	match = of_match_node(rockchip_clk_link_of_match, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	priv = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_link_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	priv->link = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	priv->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (of_property_read_string(node, "clock-output-names", &clk_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		priv->name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		priv->name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	link_info = rockchip_get_link_infos(priv->link, priv->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	priv->shift = link_info->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	priv->pname = link_info->pname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = pm_clk_create(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		goto disable_pm_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ret = pm_clk_add(&pdev->dev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret = register_clocks(priv, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		goto destroy_pm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) destroy_pm_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) disable_pm_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int rockchip_clk_link_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	pm_clk_destroy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct dev_pm_ops rockchip_clk_link_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct platform_driver rockchip_clk_link_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.name = "clock-link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.of_match_table = of_match_ptr(rockchip_clk_link_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.pm = &rockchip_clk_link_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.probe = rockchip_clk_link_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.remove = rockchip_clk_link_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int __init rockchip_clk_link_drv_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return platform_driver_register(&rockchip_clk_link_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) postcore_initcall_sync(rockchip_clk_link_drv_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void __exit rockchip_clk_link_drv_unregister(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	platform_driver_unregister(&rockchip_clk_link_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) module_exit(rockchip_clk_link_drv_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_AUTHOR("Elaine Zhang <zhangqing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("Clock driver for Niu Dependencies");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL");