^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on clk/samsung/clk-cpu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The CPU clock is typically derived from a hierarchy of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * blocks which includes mux and divider blocks. There are a number of other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * clock for CPU domain. The rates of these auxiliary clocks are related to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * CPU clock rate and this relation is usually specified in the hardware manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of the SoC or supplied after the SoC characterization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The below implementation of the CPU clock allows the rate changes of the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * clock and the corresponding rate changes of the auxillary clocks of the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * domain. The platform clock driver provides a clock register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * for each configurable rate which is then used to program the clock hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * registers to acheive a fast co-oridinated rate change for all the CPU domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * On a rate change request for the CPU clock, the rate change is propagated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * upto the PLL supplying the clock to the CPU domain clock blocks. While the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * alternate clock source. If required, the alternate clock source is divided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * down in order to keep the output clock rate within the previous OPP limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct rockchip_cpuclk: information about clock supplied to a CPU core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @hw: handle between ccf and cpu clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @alt_parent: alternate parent clock to use when switching the speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * of the primary parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @reg_base: base register for cpu-clock values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @clk_nb: clock notifier registered for changes in clock speed of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * primary parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @rate_count: number of rates in the rate_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @rate_table: pll-rates and their associated dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @reg_data: cpu-specific register settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @lock: clock lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct rockchip_cpuclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk_hw *pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_mux cpu_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct clk_ops *cpu_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk *alt_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct notifier_block clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int rate_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rockchip_cpuclk_rate_table *rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct rockchip_cpuclk_reg_data *reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define to_rockchip_cpuclk_nb(nb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) container_of(nb, struct rockchip_cpuclk, clk_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct rockchip_cpuclk *cpuclk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct rockchip_cpuclk_rate_table *rate_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpuclk->rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) for (i = 0; i < cpuclk->rate_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (rate == rate_table[i].prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return &rate_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clksel0 >>= reg_data->div_core_shift[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clksel0 &= reg_data->div_core_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return parent_rate / (clksel0 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct clk_ops rockchip_cpuclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .recalc_rate = rockchip_cpuclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct rockchip_cpuclk_rate_table *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* alternate parent is active now. set the dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!clksel->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_debug("%s: setting reg 0x%x to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __func__, clksel->reg, clksel->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(clksel->val, cpuclk->reg_base + clksel->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct rockchip_cpuclk_rate_table *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* alternate parent is active now. set the pre_muxs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!clksel->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_debug("%s: setting reg 0x%x to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __func__, clksel->reg, clksel->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(clksel->val, cpuclk->reg_base + clksel->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct rockchip_cpuclk_rate_table *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* alternate parent is active now. set the muxs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!clksel->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_debug("%s: setting reg 0x%x to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __func__, clksel->reg, clksel->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(clksel->val, cpuclk->reg_base + clksel->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_notifier_data *ndata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct rockchip_cpuclk_rate_table *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long alt_prate, alt_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* check validity of the new rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pr_err("%s: Invalid rate : %lu for cpuclk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __func__, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rockchip_boost_enable_recovery_sw_low(cpuclk->pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) alt_prate = clk_get_rate(cpuclk->alt_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock_irqsave(cpuclk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * If the old parent clock speed is less than the clock speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * of the alternate parent, then it should be ensured that at no point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * the armclk speed is more than the old_rate until the dividers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (alt_prate > ndata->old_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* calculate dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (alt_div > reg_data->div_core_mask[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_warn("%s: limiting alt-divider %lu to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __func__, alt_div, reg_data->div_core_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) alt_div = reg_data->div_core_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Change parents and add dividers in a single transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * NOTE: we do this in a single transaction so we're never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * dividing the primary parent by the extra dividers that were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * needed for the alt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __func__, alt_div, alt_prate, ndata->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < reg_data->num_cores; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg_data->div_core_shift[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cpuclk->reg_base + reg_data->core_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* select alternate parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (reg_data->mux_core_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(HIWORD_UPDATE(reg_data->mux_core_alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg_data->mux_core_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg_data->mux_core_shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cpuclk->reg_base + reg_data->mux_core_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(HIWORD_UPDATE(reg_data->mux_core_alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg_data->mux_core_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg_data->mux_core_shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpuclk->reg_base + reg_data->core_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_unlock_irqrestore(cpuclk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct clk_notifier_data *ndata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct rockchip_cpuclk_rate_table *rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pr_err("%s: Invalid rate : %lu for cpuclk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __func__, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock_irqsave(cpuclk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ndata->old_rate < ndata->new_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rockchip_cpuclk_set_dividers(cpuclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * post-rate change event, re-mux to primary parent and remove dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * NOTE: we do this in a single transaction so we're never dividing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * primary parent by the extra dividers that were needed for the alt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (reg_data->mux_core_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(HIWORD_UPDATE(reg_data->mux_core_main,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) reg_data->mux_core_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) reg_data->mux_core_shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cpuclk->reg_base + reg_data->mux_core_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(HIWORD_UPDATE(reg_data->mux_core_main,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg_data->mux_core_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) reg_data->mux_core_shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cpuclk->reg_base + reg_data->core_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rockchip_cpuclk_set_post_muxs(cpuclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* remove dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (i = 0; i < reg_data->num_cores; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg_data->div_core_shift[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cpuclk->reg_base + reg_data->core_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ndata->old_rate > ndata->new_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rockchip_cpuclk_set_dividers(cpuclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rockchip_boost_disable_recovery_sw(cpuclk->pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(cpuclk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * This clock notifier is called when the frequency of the parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * of cpuclk is to be changed. This notifier handles the setting up all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * the divider clocks, remux to temporary parent and handling the safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * frequency levels when using temporary parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __func__, event, ndata->old_rate, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (event == PRE_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else if (event == POST_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct clk *rockchip_clk_register_cpuclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct clk *parent, struct clk *alt_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) const struct rockchip_cpuclk_reg_data *reg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const struct rockchip_cpuclk_rate_table *rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int nrates, void __iomem *reg_base, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct rockchip_cpuclk *cpuclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk *clk, *cclk, *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (num_parents < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pr_err("%s: needs at least two parent clocks\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (IS_ERR(parent) || IS_ERR(alt_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pr_err("%s: invalid parent clock(s)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!cpuclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) parent_name = clk_hw_get_name(__clk_get_hw(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) init.ops = &rockchip_cpuclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* only allow rate changes when we have a rate table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* disallow automatic parent changes by ccf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) init.flags |= CLK_SET_RATE_NO_REPARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) init.flags |= CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cpuclk->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cpuclk->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cpuclk->reg_data = reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cpuclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST) && reg_data->pll_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pll_clk = clk_get_parent(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!pll_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pr_err("%s: could not lookup pll clock: (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __func__, reg_data->pll_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto free_cpuclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cpuclk->pll_hw = __clk_get_hw(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rockchip_boost_init(cpuclk->pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cpuclk->alt_parent = alt_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!cpuclk->alt_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pr_err("%s: could not lookup alternate parent: (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) __func__, reg_data->mux_core_alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto free_cpuclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = clk_prepare_enable(cpuclk->alt_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pr_err("%s: could not enable alternate parent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto free_cpuclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_err("%s: could not lookup parent clock: (%d) %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__, reg_data->mux_core_main,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) goto free_alt_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = clk_notifier_register(clk, &cpuclk->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pr_err("%s: failed to register clock notifier for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __func__, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto free_alt_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (nrates > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cpuclk->rate_count = nrates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cpuclk->rate_table = kmemdup(rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sizeof(*rates) * nrates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!cpuclk->rate_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) goto unregister_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cclk = clk_register(NULL, &cpuclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (IS_ERR(cclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pr_err("%s: could not register cpuclk %s\n", __func__, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = PTR_ERR(cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto free_rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) free_rate_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) kfree(cpuclk->rate_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unregister_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk_notifier_unregister(clk, &cpuclk->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) free_alt_parent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_disable_unprepare(cpuclk->alt_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) free_cpuclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) kfree(cpuclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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