^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) # common clock support for ROCKCHIP SoC family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) config COMMON_CLK_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) tristate "Rockchip clock controller common support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) depends on ARCH_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) default ARCH_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Say y here to enable common clock controller for Rockchip platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) if COMMON_CLK_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) config CLK_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) tristate "Rockchip PX30 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) depends on CPU_PX30 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Build the driver for PX30 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) config CLK_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) tristate "Rockchip RV1106 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) depends on CPU_RV1106 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Build the driver for RV1106 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) config CLK_RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) tristate "Rockchip RV1108 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) depends on CPU_RV1108 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Build the driver for RV1108 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) config CLK_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) tristate "Rockchip RV1126 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) depends on CPU_RV1126 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Build the driver for RV1126 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) config CLK_RK1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) tristate "Rockchip RK1808 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) depends on CPU_RK1808 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Build the driver for RK1808 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) config CLK_RK3036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) tristate "Rockchip RK3036 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) depends on CPU_RK3036 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Build the driver for RK3036 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) config CLK_RK312X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) tristate "Rockchip RK312x clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) depends on CPU_RK312X || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Build the driver for RK312x Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) config CLK_RK3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tristate "Rockchip RK3188 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) depends on CPU_RK3188 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Build the driver for RK3188 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) config CLK_RK322X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tristate "Rockchip RK322x clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) depends on CPU_RK322X || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Build the driver for RK322x Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) config CLK_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tristate "Rockchip RK3288 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) depends on CPU_RK3288 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Build the driver for RK3288 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) config CLK_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tristate "Rockchip RK3308 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) depends on CPU_RK3308 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Build the driver for RK3308 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) config CLK_RK3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tristate "Rockchip RK3328 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) depends on CPU_RK3328 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Build the driver for RK3328 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) config CLK_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tristate "Rockchip RK3368 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) depends on CPU_RK3368 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Build the driver for RK3368 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) config CLK_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tristate "Rockchip RK3399 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) depends on CPU_RK3399 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) Build the driver for RK3399 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) config CLK_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tristate "Rockchip RK3568 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) depends on CPU_RK3568 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Build the driver for RK3568 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) config CLK_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tristate "Rockchip RK3588 clock controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) depends on CPU_RK3588 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) Build the driver for RK3588 Clock Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) config ROCKCHIP_CLK_COMPENSATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bool "Rockchip Clk Compensation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Say y here to enable clk compensation(+/- 1000 ppm).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config ROCKCHIP_CLK_LINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tristate "Rockchip clock link support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) default CLK_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Say y here to enable clock link for Rockchip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config ROCKCHIP_CLK_BOOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool "Rockchip Clk Boost"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) default y if CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) Say y here to enable clk boost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) config ROCKCHIP_CLK_INV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool "Rockchip Clk Inverter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default y if !CPU_RV1126 && !CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Say y here to enable clk Inverter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) config ROCKCHIP_CLK_PVTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool "Rockchip Clk Pvtm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) default y if !CPU_RV1126 && !CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) Say y here to enable clk pvtm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) config ROCKCHIP_DDRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) config ROCKCHIP_DDRCLK_SCPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool "Rockchip DDR Clk SCPI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default y if RK3368_SCPI_PROTOCOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) select ROCKCHIP_DDRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) Say y here to enable ddr clk scpi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) config ROCKCHIP_DDRCLK_SIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool "Rockchip DDR Clk SIP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) default y if CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) select ROCKCHIP_DDRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Say y here to enable ddr clk sip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) config ROCKCHIP_DDRCLK_SIP_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool "Rockchip DDR Clk SIP V2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) default y if CPU_PX30 || CPU_RK1808 || CPU_RK312X || CPU_RK322X || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) select ROCKCHIP_DDRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) Say y here to enable ddr clk sip v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) config ROCKCHIP_PLL_RK3066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bool "Rockchip PLL Type RK3066"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default y if CPU_RK30XX || CPU_RK3188 || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CPU_RK3288 || CPU_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) Say y here to enable pll type is rk3066.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) config ROCKCHIP_PLL_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool "Rockchip PLL Type RK3399"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) default y if CPU_RK3399 || CPU_RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) Say y here to enable pll type is rk3399.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) config ROCKCHIP_PLL_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool "Rockchip PLL Type RK3588"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) default y if CPU_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Say y here to enable pll type is rk3588.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) source "drivers/clk/rockchip/regmap/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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