^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __CLK_RENESAS_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __CLK_RENESAS_CPG_MSSR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Definitions of CPG Core Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * These include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Clock outputs exported to DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - External input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - Internal CPG clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct cpg_core_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Depending on type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int parent; /* Core Clocks only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum clk_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_TYPE_IN, /* External Clock Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_TYPE_FF, /* Fixed Factor Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_TYPE_FR, /* Fixed Rate Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Custom definitions start here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CLK_TYPE_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEF_TYPE(_name, _id, _type...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .name = _name, .id = _id, .type = _type }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DEF_BASE(_name, _id, _type, _parent...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEF_TYPE(_name, _id, _type, .parent = _parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DEF_INPUT(_name, _id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEF_TYPE(_name, _id, CLK_TYPE_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEF_DIV6P1(_name, _id, _parent, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DEF_RATE(_name, _id, _rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Definitions of Module Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mssr_mod_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Convert from sparse base-100 to packed index space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEF_MOD(_name, _mod, _parent...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Convert from sparse base-10 to packed index space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DEF_MOD_STB(_name, _mod, _parent...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum clk_reg_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CLK_REG_LAYOUT_RZ_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_REG_LAYOUT_RCAR_V3U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * SoC-specific CPG/MSSR Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @early_core_clks: Array of Early Core Clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @num_early_core_clks: Number of entries in early_core_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @early_mod_clks: Array of Early Module Clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @num_early_mod_clks: Number of entries in early_mod_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @core_clks: Array of Core Clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @num_core_clks: Number of entries in core_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @last_dt_core_clk: ID of the last Core Clock exported to DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @num_total_core_clks: Total number of Core Clocks (exported + internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @mod_clks: Array of Module Clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @num_mod_clks: Number of entries in mod_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * should not be disabled without a knowledgeable driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Management, in addition to Module Clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @num_core_pm_clks: Number of entries in core_pm_clks[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @init: Optional callback to perform SoC-specific initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @cpg_clk_register: Optional callback to handle special Core Clock types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct cpg_mssr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Early Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct cpg_core_clk *early_core_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int num_early_core_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct mssr_mod_clk *early_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int num_early_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct cpg_core_clk *core_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int num_core_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int last_dt_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int num_total_core_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum clk_reg_layout reg_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct mssr_mod_clk *mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int num_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int num_hw_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Critical Module Clocks that should not be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const unsigned int *crit_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int num_crit_mod_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Core Clocks suitable for PM, in addition to the Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const unsigned int *core_pm_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int num_core_pm_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int (*init)(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk *(*cpg_clk_register)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct cpg_core_clk *core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct raw_notifier_head *notifiers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __init cpg_mssr_early_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const struct cpg_mssr_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Helpers for fixing up clock tables depending on SoC revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mssr_mod_reparent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int clk, parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int num_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int first_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int last_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int num_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const unsigned int *clks, unsigned int n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int num_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct mssr_mod_reparent *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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