Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Renesas R-Car USB2.0 clock selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on renesas-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define USB20_CLKSET0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLKSET0_INTCLK_EN	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLKSET0_PRIVATE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLKSET0_EXTAL_ONLY	(CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const struct clk_bulk_data rcar_usb2_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ .id = "ehci_ohci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ .id = "hs-usb-if", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct usb2_clock_sel_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk_bulk_data clks[ARRAY_SIZE(rcar_usb2_clocks)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct reset_control *rsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bool extal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	bool xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define to_priv(_hw)	container_of(_hw, struct usb2_clock_sel_priv, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void usb2_clock_sel_enable_extal_only(struct usb2_clock_sel_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u16 val = readw(priv->base + USB20_CLKSET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	pr_debug("%s: enter %d %d %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		 priv->extal, priv->xtal, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (priv->extal && !priv->xtal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		writew(CLKSET0_PRIVATE, priv->base + USB20_CLKSET0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int usb2_clock_sel_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct usb2_clock_sel_priv *priv = to_priv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ret = reset_control_deassert(priv->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		reset_control_assert(priv->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	usb2_clock_sel_enable_extal_only(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static void usb2_clock_sel_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct usb2_clock_sel_priv *priv = to_priv(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	usb2_clock_sel_disable_extal_only(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	reset_control_assert(priv->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * This module seems a mux, but this driver assumes a gate because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * ehci/ohci platform drivers don't support clk_set_parent() for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * If this driver acts as a gate, ehci/ohci-platform drivers don't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * any modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static const struct clk_ops usb2_clock_sel_clock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.enable = usb2_clock_sel_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.disable = usb2_clock_sel_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct of_device_id rcar_usb2_clock_sel_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ .compatible = "renesas,rcar-gen3-usb2-clock-sel" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int rcar_usb2_clock_sel_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	usb2_clock_sel_disable_extal_only(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int rcar_usb2_clock_sel_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	usb2_clock_sel_enable_extal_only(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	of_clk_del_provider(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct usb2_clock_sel_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	memcpy(priv->clks, rcar_usb2_clocks, sizeof(priv->clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clks), priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	priv->rsts = devm_reset_control_array_get(dev, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(priv->rsts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return PTR_ERR(priv->rsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	clk = devm_clk_get(dev, "usb_extal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		priv->extal = !!clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clk = devm_clk_get(dev, "usb_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		priv->xtal = !!clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!priv->extal && !priv->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_err(dev, "This driver needs usb_extal or usb_xtal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	init.name = "rcar_usb2_clock_sel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	init.ops = &usb2_clock_sel_clock_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	priv->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ret = devm_clk_hw_register(dev, &priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		goto pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		goto pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.suspend	= rcar_usb2_clock_sel_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.resume		= rcar_usb2_clock_sel_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct platform_driver rcar_usb2_clock_sel_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.name	= "rcar-usb2-clock-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.of_match_table = rcar_usb2_clock_sel_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.pm	= &rcar_usb2_clock_sel_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.probe		= rcar_usb2_clock_sel_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.remove		= rcar_usb2_clock_sel_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) builtin_platform_driver(rcar_usb2_clock_sel_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("Renesas R-Car USB2 clock selector Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL v2");