^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R-Car Gen3 Clock Pulse Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2018 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on clk-rcar-gen3.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2015 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "rcar-gen3-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPG_PLL0CR 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPG_PLL2CR 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPG_PLL4CR 0x01f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static spinlock_t cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spin_lock_irqsave(&cpg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) val &= ~clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) spin_unlock_irqrestore(&cpg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct cpg_simple_notifier {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int cpg_simple_notifier_call(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct cpg_simple_notifier *csn =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) container_of(nb, struct cpg_simple_notifier, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case PM_EVENT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) csn->saved = readl(csn->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case PM_EVENT_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(csn->saved, csn->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct cpg_simple_notifier *csn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) csn->nb.notifier_call = cpg_simple_notifier_call;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_notifier_chain_register(notifiers, &csn->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Z Clock & Z2 Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CPG_FRQCRB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CPG_FRQCRB_KICK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CPG_FRQCRC 0x000000e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct cpg_z_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *kick_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct cpg_z_clk *zclk = to_z_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = readl(zclk->reg) & zclk->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mult = 32 - (val >> __ffs(zclk->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 32 * zclk->fixed_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int cpg_z_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct cpg_z_clk *zclk = to_z_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int min_mult, max_mult, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) prate = req->best_parent_rate / zclk->fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (max_mult < min_mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mult = div64_ul(req->rate * 32ULL, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mult = clamp(mult, min_mult, max_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) req->rate = div_u64((u64)prate * mult, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct cpg_z_clk *zclk = to_z_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mult = clamp(mult, 1U, 32U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cpg_reg_modify(zclk->reg, zclk->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Set KICK bit in FRQCRB to update hardware setting and wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * clock change completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Note: There is no HW information about the worst case latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Using experimental measurements, it seems that no more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * ~10 iterations are needed, independently of the CPU rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Since this value might be dependent of external xtal rate, pll1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * rate or even the other emulation clocks rate, use 1000 as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * "super" safe value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 1000; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct clk_ops cpg_z_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .recalc_rate = cpg_z_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .determine_rate = cpg_z_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .set_rate = cpg_z_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct clk * __init cpg_z_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct cpg_z_clk *zclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!zclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) init.ops = &cpg_z_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) zclk->reg = reg + CPG_FRQCRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) zclk->kick_reg = reg + CPG_FRQCRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) zclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) zclk->mask = GENMASK(offset + 4, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk = clk_register(NULL, &zclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) kfree(zclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * SDn Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CPG_SD_STP_HCK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CPG_SD_STP_CK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ((stp_ck) ? CPG_SD_STP_CK : 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ((sd_srcfc) << 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ((sd_fc) << 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .div = (sd_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct sd_div_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct sd_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct sd_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct cpg_simple_notifier csn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int div_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int cur_div_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* SDn divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * sd_srcfc sd_fc div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *-------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * 0 0 1 (2) 1 (4) 8 : SDR50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * 1 0 2 (4) 1 (4) 16 : HS / SDR25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * 1 0 3 (8) 1 (4) 32 : NS / SDR12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * 1 0 4 (16) 1 (4) 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * 0 0 0 (1) 0 (2) 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 1 0 2 (4) 0 (2) 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 1 0 3 (8) 0 (2) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 1 0 4 (16) 0 (2) 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * NOTE: There is a quirk option to ignore the first row of the dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * table when searching for suitable settings. This is because HS400 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * early ES versions of H3 and M3-W requires a specific setting to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct sd_div_table cpg_sd_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int cpg_sd_clock_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clock->div_table[clock->cur_div_idx].val &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CPG_SD_STP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void cpg_sd_clock_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return DIV_ROUND_CLOSEST(parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clock->div_table[clock->cur_div_idx].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long calc_rate, diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < clock->div_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) clock->div_table[i].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (calc_rate < req->min_rate || calc_rate > req->max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) diff = calc_rate > req->rate ? calc_rate - req->rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) : req->rate - calc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (diff < diff_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) best_rate = calc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) diff_min = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (best_rate == ULONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct sd_clock *clock = to_sd_clock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (i = 0; i < clock->div_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (rate == DIV_ROUND_CLOSEST(parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clock->div_table[i].div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (i >= clock->div_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clock->cur_div_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clock->div_table[i].val &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct clk_ops cpg_sd_clock_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .enable = cpg_sd_clock_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .disable = cpg_sd_clock_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .is_enabled = cpg_sd_clock_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .recalc_rate = cpg_sd_clock_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .determine_rate = cpg_sd_clock_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .set_rate = cpg_sd_clock_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static u32 cpg_quirks __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct clk * __init cpg_sd_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __iomem *base, unsigned int offset, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct sd_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clock = kzalloc(sizeof(*clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) init.ops = &cpg_sd_clock_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clock->csn.reg = base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clock->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clock->div_table = cpg_sd_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (cpg_quirks & SD_SKIP_FIRST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clock->div_table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) clock->div_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(val, clock->csn.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk = clk_register(NULL, &clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto free_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cpg_simple_notifier_register(notifiers, &clock->csn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) free_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) kfree(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct rpc_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * One notifier covers both RPC and RPCD2 clocks as they are both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * controlled by the same RPCCKCR register...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct cpg_simple_notifier csn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct clk_div_table cpg_rpcsrc_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 2, 5 }, { 3, 6 }, { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct clk_div_table cpg_rpc_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct clk * __init cpg_rpc_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *base, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct rpc_clock *rpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rpc->div.reg = base + CPG_RPCCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) rpc->div.width = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rpc->div.table = cpg_rpc_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rpc->div.lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rpc->gate.reg = base + CPG_RPCCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) rpc->gate.bit_idx = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rpc->gate.lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rpc->csn.reg = base + CPG_RPCCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &rpc->div.hw, &clk_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &rpc->gate.hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) kfree(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cpg_simple_notifier_register(notifiers, &rpc->csn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct rpcd2_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct clk_fixed_factor fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct clk * __init cpg_rpcd2_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct rpcd2_clock *rpcd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!rpcd2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rpcd2->fixed.mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rpcd2->fixed.div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rpcd2->gate.reg = base + CPG_RPCCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rpcd2->gate.bit_idx = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rpcd2->gate.lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &rpcd2->fixed.hw, &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &rpcd2->gate.hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) kfree(rpcd2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static unsigned int cpg_clk_extalr __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static u32 cpg_mode __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .soc_id = "r8a7795", .revision = "ES1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .soc_id = "r8a7795", .revision = "ES1.*",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .soc_id = "r8a7795", .revision = "ES2.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .data = (void *)SD_SKIP_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .soc_id = "r8a7796", .revision = "ES1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .soc_id = "r8a7796", .revision = "ES1.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .data = (void *)SD_SKIP_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) parent = clks[core->parent & 0xffff]; /* some types use high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch (core->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case CLK_TYPE_GEN3_MAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) div = cpg_pll_config->extal_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case CLK_TYPE_GEN3_PLL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * PLL0 is a configurable multiplier clock. Register it as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * fixed factor clock for now as there's no generic multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * clock implementation and we currently have no need to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * the multiplier value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) value = readl(base + CPG_PLL0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mult = (((value >> 24) & 0x7f) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (cpg_quirks & PLL_ERRATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mult *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case CLK_TYPE_GEN3_PLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mult = cpg_pll_config->pll1_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) div = cpg_pll_config->pll1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case CLK_TYPE_GEN3_PLL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * PLL2 is a configurable multiplier clock. Register it as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * fixed factor clock for now as there's no generic multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * clock implementation and we currently have no need to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * the multiplier value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) value = readl(base + CPG_PLL2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mult = (((value >> 24) & 0x7f) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (cpg_quirks & PLL_ERRATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mult *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case CLK_TYPE_GEN3_PLL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mult = cpg_pll_config->pll3_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) div = cpg_pll_config->pll3_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case CLK_TYPE_GEN3_PLL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * PLL4 is a configurable multiplier clock. Register it as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * fixed factor clock for now as there's no generic multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * clock implementation and we currently have no need to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * the multiplier value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) value = readl(base + CPG_PLL4CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mult = (((value >> 24) & 0x7f) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (cpg_quirks & PLL_ERRATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mult *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case CLK_TYPE_GEN3_SD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return cpg_sd_clk_register(core->name, base, core->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) __clk_get_name(parent), notifiers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case CLK_TYPE_GEN3_R:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (cpg_quirks & RCKCR_CKSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct cpg_simple_notifier *csn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) csn = kzalloc(sizeof(*csn), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!csn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) csn->reg = base + CPG_RCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * RINT is default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Only if EXTALR is populated, we switch to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) value = readl(csn->reg) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (clk_get_rate(clks[cpg_clk_extalr])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) parent = clks[cpg_clk_extalr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) value |= CPG_RCKCR_CKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) writel(value, csn->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) cpg_simple_notifier_register(notifiers, csn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Select parent clock of RCLK by MD28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (cpg_mode & BIT(28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) parent = clks[cpg_clk_extalr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case CLK_TYPE_GEN3_MDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Clock selectable between two parents and two fixed dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * using a mode pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (cpg_mode & BIT(core->offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) div = core->div & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) parent = clks[core->parent >> 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) div = core->div >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case CLK_TYPE_GEN3_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return cpg_z_clk_register(core->name, __clk_get_name(parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) base, core->div, core->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case CLK_TYPE_GEN3_OSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Clock combining OSC EXTAL predivider and a fixed divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) div = cpg_pll_config->osc_prediv * core->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case CLK_TYPE_GEN3_RCKSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * Clock selectable between two parents and two fixed dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * using RCKCR.CKSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) div = core->div & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) parent = clks[core->parent >> 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) div = core->div >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case CLK_TYPE_GEN3_RPCSRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return clk_register_divider_table(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __clk_get_name(parent), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) base + CPG_RPCCKCR, 3, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) cpg_rpcsrc_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case CLK_TYPE_GEN3_RPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return cpg_rpc_clk_register(core->name, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __clk_get_name(parent), notifiers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case CLK_TYPE_GEN3_RPCD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return cpg_rpcd2_clk_register(core->name, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) __clk_get_name(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return clk_register_fixed_factor(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __clk_get_name(parent), 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int clk_extalr, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const struct soc_device_attribute *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cpg_pll_config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cpg_clk_extalr = clk_extalr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cpg_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) attr = soc_device_match(cpg_quirks_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) cpg_quirks = (uintptr_t)attr->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_lock_init(&cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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