Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * R-Car Gen2 Clock Pulse Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016 Cogent Embedded Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __CLK_RENESAS_RCAR_GEN2_CPG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) enum rcar_gen2_clk_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	CLK_TYPE_GEN2_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	CLK_TYPE_GEN2_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	CLK_TYPE_GEN2_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	CLK_TYPE_GEN2_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	CLK_TYPE_GEN2_LB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	CLK_TYPE_GEN2_ADSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	CLK_TYPE_GEN2_SDH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	CLK_TYPE_GEN2_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	CLK_TYPE_GEN2_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	CLK_TYPE_GEN2_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	CLK_TYPE_GEN2_RCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct rcar_gen2_cpg_pll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u8 extal_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u8 pll1_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u8 pll3_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u8 pll0_mult;		/* leave as zero if PLL0CR exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct raw_notifier_head *notifiers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		       unsigned int pll0_div, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif