^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R-Car Gen2 Clock Pulse Generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Cogent Embedded Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "rcar-gen2-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPG_FRQCRB 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPG_FRQCRB_KICK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPG_SDCKCR 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPG_PLL0CR 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPG_PLL0CR_STC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPG_FRQCRC 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPG_FRQCRC_ZFC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPG_ADSPCKCR 0x025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPG_RCANCKCR 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static spinlock_t cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Z Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct cpg_z_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *kick_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct cpg_z_clk *zclk = to_z_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mult = 32 - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return div_u64((u64)parent_rate * mult, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int cpg_z_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long prate = req->best_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int min_mult, max_mult, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (max_mult < min_mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mult = div64_ul(req->rate * 32ULL, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mult = clamp(mult, min_mult, max_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) req->rate = div_u64((u64)prate * mult, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cpg_z_clk *zclk = to_z_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 val, kick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mult = div64_ul(rate * 32ULL, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mult = clamp(mult, 1U, 32U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val = readl(zclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val &= ~CPG_FRQCRC_ZFC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(val, zclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Set KICK bit in FRQCRB to update hardware setting and wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * clock change completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) kick = readl(zclk->kick_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) kick |= CPG_FRQCRB_KICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(kick, zclk->kick_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Note: There is no HW information about the worst case latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Using experimental measurements, it seems that no more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * ~10 iterations are needed, independently of the CPU rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Since this value might be dependent on external xtal rate, pll1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * rate or even the other emulation clocks rate, use 1000 as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * "super" safe value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 1000; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct clk_ops cpg_z_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .recalc_rate = cpg_z_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .determine_rate = cpg_z_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .set_rate = cpg_z_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clk * __init cpg_z_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct cpg_z_clk *zclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!zclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) init.ops = &cpg_z_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) zclk->reg = base + CPG_FRQCRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) zclk->kick_reg = base + CPG_FRQCRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) zclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk = clk_register(NULL, &zclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) kfree(zclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct clk * __init cpg_rcan_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk_fixed_factor *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) fixed->mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fixed->div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kfree(fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) gate->reg = base + CPG_RCANCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) gate->bit_idx = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) gate->flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gate->lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &fixed->hw, &clk_fixed_factor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &gate->hw, &clk_gate_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) kfree(fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* ADSP divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct clk_div_table cpg_adsp_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 10, 36 }, { 11, 48 }, { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct clk * __init cpg_adsp_clk_register(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) div->reg = base + CPG_ADSPCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) div->width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) div->table = cpg_adsp_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) div->lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) gate->reg = base + CPG_ADSPCKCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) gate->bit_idx = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gate->flags = CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) gate->lock = &cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &div->hw, &clk_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &gate->hw, &clk_gate_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* SDHI divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct clk_div_table cpg_sdh_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct clk_div_table cpg_sd01_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static unsigned int cpg_pll0_div __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static u32 cpg_mode __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static u32 cpg_quirks __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .soc_id = "r8a77470",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .data = (void *)SD_SKIP_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct clk_div_table *table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) parent = clks[core->parent];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) parent_name = __clk_get_name(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (core->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* R-Car Gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case CLK_TYPE_GEN2_MAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) div = cpg_pll_config->extal_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case CLK_TYPE_GEN2_PLL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * PLL0 is a configurable multiplier clock except on R-Car
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * V2H/E2. Register the PLL0 clock as a fixed factor clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * now as there's no generic multiplier clock implementation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * we currently have no need to change the multiplier value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mult = cpg_pll_config->pll0_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) div = cpg_pll0_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 pll0cr = readl(base + CPG_PLL0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CPG_PLL0CR_STC_SHIFT) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case CLK_TYPE_GEN2_PLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mult = cpg_pll_config->pll1_mult / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case CLK_TYPE_GEN2_PLL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mult = cpg_pll_config->pll3_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case CLK_TYPE_GEN2_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return cpg_z_clk_register(core->name, parent_name, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case CLK_TYPE_GEN2_LB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) div = cpg_mode & BIT(18) ? 36 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case CLK_TYPE_GEN2_ADSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return cpg_adsp_clk_register(core->name, parent_name, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case CLK_TYPE_GEN2_SDH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) table = cpg_sdh_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case CLK_TYPE_GEN2_SD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) table = cpg_sd01_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (cpg_quirks & SD_SKIP_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) shift = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case CLK_TYPE_GEN2_SD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) table = cpg_sd01_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (cpg_quirks & SD_SKIP_FIRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case CLK_TYPE_GEN2_QSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 8 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case CLK_TYPE_GEN2_RCAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return cpg_rcan_clk_register(core->name, parent_name, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return clk_register_fixed_factor(NULL, core->name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return clk_register_divider_table(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) base + CPG_SDCKCR, shift, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0, table, &cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int pll0_div, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct soc_device_attribute *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cpg_pll_config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cpg_pll0_div = pll0_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cpg_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) attr = soc_device_match(cpg_quirks_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cpg_quirks = (uintptr_t)attr->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) spin_lock_init(&cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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