^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on r8a7795-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2015 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum rcar_r8a779a0_clk_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CLK_TYPE_R8A779A0_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_TYPE_R8A779A0_PLL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct rcar_r8a779a0_cpg_pll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 extal_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 pll1_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 pll1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 pll5_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 pll5_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 osc_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CLK_EXTALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CLK_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_PLL20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CLK_PLL21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CLK_PLL30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CLK_PLL31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CLK_PLL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_PLL20_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_PLL21_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_PLL30_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CLK_PLL31_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_PLL5_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_PLL5_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CLK_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CLK_S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_SDSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CLK_RPCSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CLK_OCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DEF_PLL(_name, _id, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .offset = _offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (_parent0) << 16 | (_parent1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .div = (_div0) << 16 | (_div1), .offset = _md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEF_OSC(_name, _id, _parent, _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEF_INPUT("extal", CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEF_INPUT("extalr", CLK_EXTALR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEF_PLL(".pll20", CLK_PLL20, 0x0834),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEF_PLL(".pll21", CLK_PLL21, 0x0838),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEF_PLL(".pll30", CLK_PLL30, 0x083c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEF_PLL(".pll31", CLK_PLL31, 0x0840),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEF_RATE(".oco", CLK_OCO, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static spinlock_t cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static unsigned int cpg_clk_extalr __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static u32 cpg_mode __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) parent = clks[core->parent & 0xffff]; /* some types use high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (core->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case CLK_TYPE_R8A779A0_MAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) div = cpg_pll_config->extal_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case CLK_TYPE_R8A779A0_PLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mult = cpg_pll_config->pll1_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) div = cpg_pll_config->pll1_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case CLK_TYPE_R8A779A0_PLL2X_3X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) value = readl(base + core->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mult = (((value >> 24) & 0x7f) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case CLK_TYPE_R8A779A0_PLL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mult = cpg_pll_config->pll5_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) div = cpg_pll_config->pll5_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case CLK_TYPE_R8A779A0_MDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Clock selectable between two parents and two fixed dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * using a mode pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (cpg_mode & BIT(core->offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) div = core->div & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) parent = clks[core->parent >> 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) div = core->div >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case CLK_TYPE_R8A779A0_OSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Clock combining OSC EXTAL predivider and a fixed divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) div = cpg_pll_config->osc_prediv * core->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return clk_register_fixed_factor(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __clk_get_name(parent), 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 14 13 (MHz) 21 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * 0 1 20 x 1 x106 x180 x106 x120 x160 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (((md) & BIT(13)) >> 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 1, 128, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 1, 106, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0, 0, 0, 0, 0, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 2, 128, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int __init r8a779a0_cpg_mssr_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) error = rcar_rst_read_mode_pins(&cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cpg_clk_extalr = CLK_EXTALR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spin_lock_init(&cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .core_clks = r8a779a0_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .mod_clks = r8a779a0_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_hw_mod_clks = 15 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .init = r8a779a0_cpg_mssr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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