^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on r8a7795-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "rcar-gen3-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CLK_EXTALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CLK_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_PLL1_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CLK_S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CLK_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CLK_S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLK_S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CLK_SDSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CLK_RPCSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CLK_OCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEF_INPUT("extal", CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEF_INPUT("extalr", CLK_EXTALR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEF_RATE(".oco", CLK_OCO, 32768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_RPCSRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) R8A77980_CLK_RPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEF_MOD("cmt3", 300, R8A77980_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEF_MOD("cmt2", 301, R8A77980_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEF_MOD("cmt1", 302, R8A77980_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEF_MOD("cmt0", 303, R8A77980_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEF_MOD("rwdt", 402, R8A77980_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEF_MOD("thermal", 522, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MOD_CLK_ID(402), /* RWDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MOD_CLK_ID(408), /* INTC-AP (GIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * MD EXTAL PLL2 PLL1 PLL3 OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * 14 13 (MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * 0 0 16.66 x 1 x240 x192 x192 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 0 1 20 x 1 x200 x160 x160 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * 1 0 27 x 1 x148 x118 x118 /26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 1 1 33.33 / 2 x240 x192 x192 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (((md) & BIT(13)) >> 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 1, 192, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 1, 160, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 1, 118, 1, 118, 1, 26, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 2, 192, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init r8a77980_cpg_mssr_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 cpg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) error = rcar_rst_read_mode_pins(&cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .core_clks = r8a77980_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .num_core_clks = ARRAY_SIZE(r8a77980_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .mod_clks = r8a77980_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_hw_mod_clks = 12 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Critical Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .crit_mod_clks = r8a77980_crit_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .init = r8a77980_cpg_mssr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cpg_clk_register = rcar_gen3_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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