Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017-2018 Cogent Embedded Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on r8a7795-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "rcar-gen3-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CPG_SD0CKCR		0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) enum r8a77970_clk_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	CLK_TYPE_R8A77970_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	CLK_EXTALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	CLK_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	CLK_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	CLK_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	CLK_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	CLK_PLL1_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static spinlock_t cpg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct clk_div_table cpg_sd0h_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const struct clk_div_table cpg_sd0_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{  0,  0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DEF_INPUT("extal",	CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	DEF_INPUT("extalr",	CLK_EXTALR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DEF_FIXED(".pll1_div4",	CLK_PLL1_DIV4,	CLK_PLL1_DIV2,	2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DEF_FIXED("ztr",	R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DEF_FIXED("ztrd2",	R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DEF_FIXED("zt",		R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DEF_FIXED("zx",		R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	DEF_FIXED("s1d1",	R8A77970_CLK_S1D1,  CLK_PLL1_DIV2,  4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	DEF_FIXED("s1d2",	R8A77970_CLK_S1D2,  CLK_PLL1_DIV2,  8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	DEF_FIXED("s1d4",	R8A77970_CLK_S1D4,  CLK_PLL1_DIV2, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	DEF_FIXED("s2d1",	R8A77970_CLK_S2D1,  CLK_PLL1_DIV2,  6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DEF_FIXED("s2d2",	R8A77970_CLK_S2D2,  CLK_PLL1_DIV2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DEF_FIXED("s2d4",	R8A77970_CLK_S2D4,  CLK_PLL1_DIV2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		 CLK_PLL1_DIV2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DEF_BASE("sd0",	R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	DEF_FIXED("rpc",	R8A77970_CLK_RPC,   CLK_PLL1_DIV2,  5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	DEF_FIXED("rpcd2",	R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DEF_FIXED("cl",		R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DEF_FIXED("cp",		R8A77970_CLK_CP,    CLK_EXTAL,	    2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DEF_FIXED("cpex",	R8A77970_CLK_CPEX,  CLK_EXTAL,	    2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	DEF_DIV6P1("canfd",	R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DEF_DIV6P1("mso",	R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	DEF_DIV6P1("csi0",	R8A77970_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	DEF_FIXED("osc",	R8A77970_CLK_OSC,   CLK_PLL1_DIV2, 12*1024, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	DEF_FIXED("r",		R8A77970_CLK_R,	    CLK_EXTALR,	   1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	DEF_MOD("tmu4",			 121,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	DEF_MOD("tmu3",			 122,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	DEF_MOD("tmu2",			 123,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	DEF_MOD("tmu1",			 124,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	DEF_MOD("tmu0",			 125,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	DEF_MOD("ivcp1e",		 127,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	DEF_MOD("scif4",		 203,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	DEF_MOD("scif3",		 204,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	DEF_MOD("scif1",		 206,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	DEF_MOD("scif0",		 207,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	DEF_MOD("msiof3",		 208,	R8A77970_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	DEF_MOD("msiof2",		 209,	R8A77970_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	DEF_MOD("msiof1",		 210,	R8A77970_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	DEF_MOD("msiof0",		 211,	R8A77970_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	DEF_MOD("mfis",			 213,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	DEF_MOD("sys-dmac2",		 217,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	DEF_MOD("sys-dmac1",		 218,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	DEF_MOD("cmt3",			 300,	R8A77970_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	DEF_MOD("cmt2",			 301,	R8A77970_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	DEF_MOD("cmt1",			 302,	R8A77970_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	DEF_MOD("cmt0",			 303,	R8A77970_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	DEF_MOD("tpu0",			 304,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	DEF_MOD("sd-if",		 314,	R8A77970_CLK_SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	DEF_MOD("rwdt",			 402,	R8A77970_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	DEF_MOD("intc-ex",		 407,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	DEF_MOD("intc-ap",		 408,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	DEF_MOD("hscif3",		 517,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	DEF_MOD("hscif2",		 518,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	DEF_MOD("hscif1",		 519,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	DEF_MOD("hscif0",		 520,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	DEF_MOD("thermal",		 522,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	DEF_MOD("pwm",			 523,	R8A77970_CLK_S2D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	DEF_MOD("fcpvd0",		 603,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	DEF_MOD("vspd0",		 623,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	DEF_MOD("csi40",		 716,	R8A77970_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	DEF_MOD("du0",			 724,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	DEF_MOD("lvds",			 727,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	DEF_MOD("vin3",			 808,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	DEF_MOD("vin2",			 809,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	DEF_MOD("vin1",			 810,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	DEF_MOD("vin0",			 811,	R8A77970_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	DEF_MOD("etheravb",		 812,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	DEF_MOD("gpio5",		 907,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	DEF_MOD("gpio4",		 908,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	DEF_MOD("gpio3",		 909,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	DEF_MOD("gpio2",		 910,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	DEF_MOD("gpio1",		 911,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	DEF_MOD("gpio0",		 912,	R8A77970_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	DEF_MOD("can-fd",		 914,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	DEF_MOD("rpc-if",		 917,	R8A77970_CLK_RPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	DEF_MOD("i2c4",			 927,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	DEF_MOD("i2c3",			 928,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	DEF_MOD("i2c2",			 929,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	DEF_MOD("i2c1",			 930,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	DEF_MOD("i2c0",			 931,	R8A77970_CLK_S2D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	MOD_CLK_ID(402),	/* RWDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  *   MD		EXTAL		PLL0	PLL1	PLL3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * 14 13 19	(MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  *-------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * 0  0  0	16.66 x 1	x192	x192	x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * 0  0  1	16.66 x 1	x192	x192	x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * 0  1  0	20    x 1	x160	x160	x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * 0  1  1	20    x 1	x160	x160	x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * 1  0  0	27    / 2	x236	x236	x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * 1  0  1	27    / 2	x236	x236	x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * 1  1  0	33.33 / 2	x192	x192	x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * 1  1  1	33.33 / 2	x192	x192	x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					 (((md) & BIT(13)) >> 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 					 (((md) & BIT(19)) >> 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ 1,		192,	1,	96,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ 1,		192,	1,	80,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ 1,		160,	1,	80,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ 1,		160,	1,	66,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 2,		236,	1,	118,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 2,		236,	1,	98,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ 2,		192,	1,	96,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ 2,		192,	1,	80,	1,	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int __init r8a77970_cpg_mssr_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 cpg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	error = rcar_rst_read_mode_pins(&cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	spin_lock_init(&cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct clk **clks, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct raw_notifier_head *notifiers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	const struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	switch (core->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case CLK_TYPE_R8A77970_SD0H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		table = cpg_sd0h_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	case CLK_TYPE_R8A77970_SD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		table = cpg_sd0_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		shift = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 						  notifiers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	parent = clks[core->parent];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return ERR_CAST(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return clk_register_divider_table(NULL, core->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					  __clk_get_name(parent), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					  base + CPG_SD0CKCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 					  shift, 4, 0, table, &cpg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.core_clks = r8a77970_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.mod_clks = r8a77970_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.num_hw_mod_clks = 12 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Critical Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.crit_mod_clks = r8a77970_crit_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.init = r8a77970_cpg_mssr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.cpg_clk_register = r8a77970_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };