^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018-2019 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on clk-rcar-gen3.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2015 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "rcar-gen3-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CLK_EXTALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_PLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CLK_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_PLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CLK_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CLK_PLL1_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CLK_S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLK_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CLK_S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CLK_S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CLK_SDSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CLK_SSPSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CLK_RPCSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CLK_RINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEF_INPUT("extal", CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEF_INPUT("extalr", CLK_EXTALR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_RPCSRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) R8A7795_CLK_RPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEF_MOD("cmt3", 300, R8A7795_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEF_MOD("cmt2", 301, R8A7795_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEF_MOD("cmt1", 302, R8A7795_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEF_MOD("cmt0", 303, R8A7795_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEF_MOD("rwdt", 402, R8A7795_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEF_MOD("thermal", 522, R8A7795_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MOD_CLK_ID(402), /* RWDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MOD_CLK_ID(408), /* INTC-AP (GIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 14 13 19 17 (MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * 0 0 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * 0 1 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 1 0 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * 1 1 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (((md) & BIT(13)) >> 11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (((md) & BIT(19)) >> 18) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (((md) & BIT(17)) >> 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 1, 192, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 1, 192, 1, 128, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 1, 192, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 1, 160, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 1, 160, 1, 106, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 1, 160, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 1, 128, 1, 128, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 1, 128, 1, 84, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 1, 128, 1, 128, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 2, 192, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 2, 192, 1, 128, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 2, 192, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct soc_device_attribute r8a7795es1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .soc_id = "r8a7795", .revision = "ES1.*" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Fixups for R-Car H3 ES1.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MOD_CLK_ID(326), /* USB-DMAC3-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MOD_CLK_ID(329), /* USB-DMAC3-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MOD_CLK_ID(700), /* EHCI/OHCI3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MOD_CLK_ID(705), /* HS-USB-IF3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Fixups for R-Car H3 ES2.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MOD_CLK_ID(117), /* FDP1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MOD_CLK_ID(327), /* USB3-IF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MOD_CLK_ID(600), /* FCPVD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MOD_CLK_ID(609), /* FCPVI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MOD_CLK_ID(613), /* FCPF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MOD_CLK_ID(616), /* FCPCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MOD_CLK_ID(617), /* FCPCI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MOD_CLK_ID(620), /* VSPD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MOD_CLK_ID(629), /* VSPI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MOD_CLK_ID(713), /* CSI21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int __init r8a7795_cpg_mssr_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 cpg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) error = rcar_rst_read_mode_pins(&cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!cpg_pll_config->extal_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (soc_device_match(r8a7795es1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) cpg_core_nullify_range(r8a7795_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ARRAY_SIZE(r8a7795_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mssr_mod_nullify(r8a7795_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARRAY_SIZE(r8a7795_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) r8a7795es1_mod_nullify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ARRAY_SIZE(r8a7795es1_mod_nullify));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mssr_mod_reparent(r8a7795_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ARRAY_SIZE(r8a7795_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) r8a7795es1_mod_reparent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ARRAY_SIZE(r8a7795es1_mod_reparent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mssr_mod_nullify(r8a7795_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ARRAY_SIZE(r8a7795_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) r8a7795es2_mod_nullify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ARRAY_SIZE(r8a7795es2_mod_nullify));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .core_clks = r8a7795_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .mod_clks = r8a7795_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_hw_mod_clks = 12 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Critical Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .crit_mod_clks = r8a7795_crit_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .init = r8a7795_cpg_mssr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cpg_clk_register = rcar_gen3_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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