^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on r8a7796-cpg-mssr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2016 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/soc/renesas/rcar-rst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "renesas-cpg-mssr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "rcar-gen3-cpg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum clk_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Core Clock Outputs exported to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* External Input Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CLK_EXTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) CLK_EXTALR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CLK_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CLK_PLL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLK_PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_PLL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_PLL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_PLL1_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CLK_PLL1_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CLK_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CLK_S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CLK_S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLK_SDSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CLK_RINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MOD_CLK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* External Clock Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEF_INPUT("extal", CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEF_INPUT("extalr", CLK_EXTALR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Internal Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Core Clock Outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MOD_CLK_ID(402), /* RWDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MOD_CLK_ID(408), /* INTC-AP (GIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * CPG Clock Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 14 13 19 17 (MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * 0 0 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * 0 1 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * 1 0 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 1 1 1 0 Prohibited setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (((md) & BIT(13)) >> 11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (((md) & BIT(19)) >> 18) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (((md) & BIT(17)) >> 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 1, 192, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 1, 192, 1, 128, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 1, 192, 1, 192, 1, 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 1, 160, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 1, 160, 1, 106, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 1, 160, 1, 160, 1, 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 1, 128, 1, 128, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 1, 128, 1, 84, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 1, 128, 1, 128, 1, 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 2, 192, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 2, 192, 1, 128, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0, /* Prohibited setting */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 2, 192, 1, 192, 1, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int __init r8a774b1_cpg_mssr_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 cpg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) error = rcar_rst_read_mode_pins(&cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!cpg_pll_config->extal_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Core Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .core_clks = r8a774b1_core_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .num_core_clks = ARRAY_SIZE(r8a774b1_core_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .last_dt_core_clk = LAST_DT_CORE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .num_total_core_clks = MOD_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .mod_clks = r8a774b1_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .num_hw_mod_clks = 12 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Critical Module Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .crit_mod_clks = r8a774b1_crit_mod_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .init = r8a774b1_cpg_mssr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .cpg_clk_register = rcar_gen3_cpg_clk_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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